Am79C971
177
P R E L I M I N A R Y
The STVAL value is interpreted
as an unsigned number with a
resolution of 12.8
μ
s. For in-
stance, a value of 122 ms would
be programmed with a value of
9531 (253Bh). A value of 0 is un-
defined and will result in erratic
behavior.
Read and write accessible al-
ways. STVAL is set to FFFFh af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
BCR32: MII Control and Status Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
ANTST
Reserved. Reserved for manu-
facturing tests. Written as 0 and
read as undefined.
Note
: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
ANTST is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
14
MIIPD
MII PHY Detect. MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updat-
ed whenever there is no manage-
ment operation in progress on the
MII interface. When a manage-
ment operation begins on the in-
terface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuous-
ly updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quies-
cent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the Auto Select bit
(ASEL, BCR2, bit 1) is a 1 and the
MIIPD bit is a 1, the MII port is se-
lected. Any transition on the MI-
IPD bit will set the MIIPDINT bit in
CSR7, bit 1.
Read accessible always. MIIPD
is read only. Write operations are
ignored.
13-12 FMDC
Fast Management Data Clock.
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying
must also be able to accept man-
agement frames at the new clock
rate. When FMDC is set to 1h, the
MII Management Data Clock will
run at 5 MHz. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying
must also be able to accept man-
agement frames at the new clock
rate. When FMDC is set to 0h, the
MII Management Data Clock will
run at 2.5 MHz and will be fully
compliant to IEEE 802.3u stan-
dards.
external
PHY
external
PHY
Read/Write accessible always.
FMDC is set to 0 during
H_RESET, and is unaffected by
S_RESET and the STOP bit
11
APEP
MII Auto-Poll External PHY.
APEP when set to 1 the
Am79C971 controller will poll the
MII status register in the external
PHY. This feature allows the soft-
ware driver or upper layers to see
any changes in the status of the
external PHY. An interrupt when
enabled is generated when the
contents of the new status is dif-
ferent from the previous status.
Auto-Poll will not function when
the internal PHY is selected.
Table 40.
Fast Management Data Clock
2.5 MHz
5 MHz
10 MHz
Reserved
FMDC Values
FMDC
00
01
10
11