參數(shù)資料
型號(hào)： AM79C971
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述： PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線
文件頁(yè)數(shù)： 174/265頁(yè)
文件大小： 3190K
代理商： AM79C971
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174
Am79C971
P R E L I M I N A R Y
Note
: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
PTR_TST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
14
LOLATRX
Low Latency Receive. When the
LOLATRX bit is set to 1, the
Am79C971 controller will switch
to an architecture applicable to
cut-through
switches.
Am79C971 controller will assert a
receive frame DMA after only 16
bytes of the current receive frame
has been received regardless of
where the RCVFW (CSR80, bits
13-12) are set. The watermark is
a fixed value and cannot be
changed. The receive FIFOs will
be in NO_SRAM mode while all
transmit traffic is buffered through
the external SRAM. This bit is
only valid and the low latency re-
ceive only enabled when the
SRAM_SIZE (BCR25, bits 7-0)
bits are non-zero. SRAM_BND
(BCR26, bits 7-0) has no mean-
ing when the Am79C971 control-
ler is in the Low Latency mode.
See the section on
SRAM Config-
uration
for more details.
The
When the LOLATRX bit is set to
0, the Am79C971 controller will
return to a normal receive config-
uration. The runt packet accept
bit (RPA, CSR124, bit 3) must be
set when LOLATRX is set.
CAUTION: To provide data in-
tegrity when switching into
and out of the low latency
mode, DO NOT SET the
FASTSPNDE (CSR7, bit 15) bit
when setting the SPND bit. Re-
ceive frames WILL be overwrit-
ten
and
the
controller may give erratic be-
havior when it is enable again.
The minimum allowed number
of
pages
is
Am79C971 controller will not
operate correctly in the LOLA-
TRX mode with less than four
pages of memory.
Am79C971
four.
The
Read/Write accessible only when
the STOP bit is set. LOLATRX is
cleared to 0 after H_RESET or
S_RESET and is unaffected by
STOP.
13-6
RES
Reserved locations. Written as
zeros and read as undefined.
5-3
EBCS
Expansion Bus Clock Source.
These bits are used to select the
source of the fundamental clock
to drive the SRAM and Expansion
ROM access cycles. Table 38
shows the selected clock source
for the various values of EBCS.
Note that the actual frequency
that the Expansion Bus access
cycles run at is a function of both
the
EBCS
and
(BCR27, bits 2-0) bit field set-
tings. When EBCS is set to either
the PCI clock or the XTAL clock,
no external clock source is re-
quired as the clocks are routed in-
ternally and the EBCLK pin
should be pulled to VDD through
a resistor.
CLK_FAC
Read accessible always; write
accessible only when the STOP
bit is set. EBCS is set to 000b
(PCI
clock
selected) during
H_RESET and is unaffected by
S_RESET or the STOP bit.
Note
: The clock frequency driv-
ing the Expansion Bus access cy-
cles that results from the settings
of the EBCS and CLK FAC bits
must not exceed 33 MHz at any
time. When EBCS is set to either
the PCI clock or the XTAL clock,
no external clock source is re-
quired because the clocks are
routed internally and the EBCLK
pin should be pulled to VDD
through a resistor.
Table 38.
Expansion Bus Clock Source
CLK pin (PCI Clock)
XTAL1 and XTAL2 pins (20-MHz clock)
EBCLK pin
Reserved
Reserved
EBCS Values
EBCS
000
001
010
011
1XX
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參數(shù)描述
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