- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1909 > CS8952-IQZ (Cirrus Logic Inc)IC TXRX 100/10 PHY 100TQFP PDF資料下載
參數(shù)資料
| 型號： | CS8952-IQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX 100/10 PHY 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1208 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
23
DS206F1
RX_CLK, RX_DV, COL, and CRS) onto a shared,
external repeater system bus.
3.1.3
10BASE-T MII Application
The digital interface used in this mode is the same
as that used in the 100BASE-X MII mode except
that TX_CLK and RX_CLK are nominally
2.5 MHz.
The CS8952 includes a full-featured 10BASE-T in-
terface, as described in the following sections.
3.1.3.1
Full and Half Duplex operation
The 10BASE-T function supports full and half du-
plex operation as determined by pins AN[1:0]
and/or the corresponding MII register bits. (See Ta-
ble 5).
3.1.3.2
Collision Detection
If half duplex operation is selected, the CS8952 de-
tects a 10BASE-T collision whenever the receiver
and transmitter are active simultaneously. When a
collision is present, the collision is reported on pin
COL. Collision detection is undefined for full-du-
plex operation.
3.1.3.3
Jabber
The jabber timer monitors the transmitter and dis-
ables the transmission if the transmitter is active for
greater than approximately 105 ms. The transmitter
stays disabled until approximately 406 ms after the
internal transmit request is no longer enabled.
3.1.3.4
Link Pulses
To prevent disruption of network operation due to a
faulty link segment, the CS8952 continually moni-
tors the 10BASE-T receive pair (RXD+ and RXD-)
for packets and link pulses. After each packet or link
pulse is received, an internal Link-Loss timer is
started. As long as a packet or link pulse is received
before the Link-Loss timer finishes (between 50 and
100 ms), the CS8952 maintains normal operation. If
no receive activity is detected, the CS8952 disables
packet transmission to prevent “blind” transmis-
sions onto the network (link pulses are still sent
while packet transmission is disabled). To reactivate
transmission, the receiver must detect a single pack-
et (the packet itself is ignored), or two normal link
pulses separated by more than 6 ms and no more
than 50 ms.
The CS8952 automatically checks the polarity of
the receive half of the twisted pair cable. To detect
a reversed pair, the receiver examines received link
pulses and the End-of-Frame (EOF) sequence of
incoming packets. If it detects at least one reversed
link pulse and at least four frames in a row with
negative polarity after the EOF, the receive pair is
considered reversed. If the polarity is reversed and
bit 1 of the 10BASE-T Configuration Register (ad-
dress 1Ch), is set, the CS8952 automatically cor-
rects a reversal.
In the absence of transmit packets, the transmitter
generates
link
pulses
in
accordance
with
Section 14.2.1.1 of the Ethernet standard. Trans-
mitted link pulses are positive pulses, one bit time
wide, typically generated at a rate of one every
16 ms. The 16 ms timer also starts whenever the
transmitter completes an End-of-Frame (EOF) se-
quence. Thus, a link pulse will be generated 16 ms
after an EOF unless there is another transmitted
packet.
3.1.3.5
Receiver Squelch
The 10BASE-T squelch circuit determines when
valid data is present on the RXD+/RXD- pair. In-
coming signals passing through the receive filter
are tested by the squelch circuit. Any signal with
amplitude less than the squelch threshold (either
positive or negative, depending on polarity) is re-
jected.
3.1.3.6
10BASE-T Loopback
When Loopback is selected, the TXD[3:0] pins are
looped back into the RXD[3:0] pins through the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8CLED04DOCD1-56LTXI | IC POWERPSOC DEBUG 4CH 1A 56VQFN |
| CYG2217 | IC MOD PHONE LINE WIRE 1.07" PCB |
| DAC312ER | IC DAC 12BIT MULT HS 20-CDIP |
| DAC8143FPZ | IC DAC 12BIT DAISYCHAIN 16DIP |
| DAC8228FSZ | IC DAC 8BIT DUAL V-OUT 20SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8952-IQZR | 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| CS8952T | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-CQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQR | 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。