- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1909 > CS8952-IQZ (Cirrus Logic Inc)IC TXRX 100/10 PHY 100TQFP PDF資料下載
參數(shù)資料
| 型號： | CS8952-IQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 18/81頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX 100/10 PHY 100TQFP |
| 標準包裝： | 90 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1208 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
25
DS206F1
Auto-Negotiation encapsulates information within
a burst of closely spaced Link Integrity Test Pulses,
referred to as a Fast Link Pulse (FLP) Burst. The
FLP Burst consists of a series of Link Integrity
Pulses which form an alternating clock / data se-
quence. Extraction of the data bits from the FLP
Burst yields a Link Code Word which identifies the
capability of the remote device.
In order to support legacy 10 and 100 Mb/s devic-
es, the CS8952 also supports parallel detection. In
parallel detection, the CS8952 monitors activity on
the media to determine the capability of the link
partner even without auto-negotiation having oc-
curred.
3.3
Reset Operation
Reset occurs in response to six different conditions:
1) There is a chip-wide reset whenever the RE-
SET pin is high for at least 200 ns. During a
chip-wide reset, all circuitry and registers in the
CS8952 are reset.
2) When power is applied, the CS8952 maintains
reset until the voltage at the VDD supply pins
reaches approximately 3.6 V. The CS8952
comes out of reset once VDD is greater than ap-
proximately 3.6 V and the crystal oscillator has
stabilized.
3) There is a chip-wide reset whenever the RE-
SET bit (bit 15 of the Basic Mode Control Reg-
ister (address 00h)) is set.
4) Digital circuitry is reset whenever bit 0 of the
PCS Sub-Layer Configuration Register (ad-
dress 17h) is set. Analog circuitry is unaffected.
5) Analog circuitry is reset and recalibrated when-
ever the CS8952 enters or exits the power-
down state, as requested by pin PWRDN.
6) Analog circuitry is reset and recalibrated when-
ever the CS8952 changes between 10 Mb/s and
100 Mb/s modes.
After a reset, the CS8952 latches the signals on var-
ious input pins in order to initialize key registers
and goes through a self configuration. This in-
cludes calibrating on-chip analog circuitry. Time
required for the reset calibration is typically 40 ms.
External circuitry may access registers internal to
the CS8952 during this time. Reset and calibration
complete is indicated when bit 15 of the Basic
Mode Control Register (address 00h) is clear.
3.4
LED Indicators
The LEDx, SPD100, and SPD10 output pins pro-
vide status information that can be used to drive
LEDs or can be used as inputs to external control
circuitry. Indication options include: receive activ-
ity, transmit activity, collision, carrier sense, polar-
ity OK, descrambler synchronization status, auto-
negotiation status, speed (10 vs. 100), and duplex
mode.
4. MEDIA INDEPENDENT INTERFACE
(MII)
The Media Independent Interface (MII) provides a
simple interconnect to an external Media Access
Controller (MAC). This connection may be chip to
chip, motherboard to daughterboard, or a connec-
tion between two assemblies attached by a limited
length of shielded cable and an appropriate connec-
tor.
The MII interface uses the following pins:
AN1
AN0
Forced/
Auto
Speed
(Mb/s)
Full/Half
Duplex
Low
Floating
Forced
10
Half
High
Floating
Forced
10
Full
Floating
Low
Forced
100
Half
Floating
High
Forced
100
Full
Floating
Auto-Neg
100/10
Full/Half
Low
Auto-Neg
10
Half
Low
High
Auto-Neg
10
Full
High
Low
Auto-Neg
100
Half
High
Auto-Neg
100
Full
Table 5.
相關PDF資料 |
PDF描述 |
|---|---|
| CY8CLED04DOCD1-56LTXI | IC POWERPSOC DEBUG 4CH 1A 56VQFN |
| CYG2217 | IC MOD PHONE LINE WIRE 1.07" PCB |
| DAC312ER | IC DAC 12BIT MULT HS 20-CDIP |
| DAC8143FPZ | IC DAC 12BIT DAISYCHAIN 16DIP |
| DAC8228FSZ | IC DAC 8BIT DUAL V-OUT 20SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS8952-IQZR | 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| CS8952T | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-CQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQR | 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。