6.1 Basic Mode Control Register - Address 00h 15 14 13 12 11 10 9 8 Soft" />
參數(shù)資料
型號: CS8952-IQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 25/81頁
文件大小: 0K
描述: IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
規(guī)程: MII
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 759 (CN2011-ZH PDF)
其它名稱: 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
31
DS206F1
6.1
Basic Mode Control Register - Address 00h
15
14
13
12
11
10
9
8
Software
Reset
Loopback
Speed
Selection
Auto-Neg
Enable
Power Down
Isolate
Restart
Auto-Neg
Duplex Mode
7654321
0
Collision Test
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Software Reset
Read/Set
0
Setting this bit performs a chip-wide reset. All status
and control registers are set to their default states,
and the analog circuitry is re-calibrated. This bit is an
Act-Once bit which is cleared once the reset and re-
calibration have completed.
This bit will also be set automatically while the analog
circuitry is reset and re-calibrated during mode
changes.
14
Loopback
Read/Write 0
When set, the CS8952 is placed in a loop back
mode. Any data sent on the transmit data path is
returned on the receive data path. Loopback mode is
entered regardless of whether 10 Mb/s or 100 Mb/s
operation has been configured.
This bit will be set upon the assertion of the LPBK
pin, and will be automatically cleared upon its deas-
sertion.
13
Speed Selection
Read/Write If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
When bit 12 is clear, setting this bit configures the
CS8952 for 100 Mb/s operation. Clearing this bit sets
the configuration at 10 Mb/s. When bit 12 is set, this
bit is ignored.
12
Auto-Neg Enable
Read/Write If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
Setting this bit enables the auto-negotiation process.
When this bit is set, bits 13 and 8 have no affect on
the link configuration. The link configuration is deter-
mined by the auto-negotiation process. Clearing this
bit disables auto-negotiation.
11
Power Down
Read/Write 0
When this bit is set, the CS8952 enters a low power
consumption state. Clearing this bit allows normal
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
10
Isolate
Read/Write If PHYAD =
00000, reset to 1;
otherwise reset to
the value on the
ISODEF pin
Setting this bit causes the MII data path to be electri-
cally isolated by tri-stating all data outputs (i.e.
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL,
and CRS). In addition the CS8952 will not respond to
the TXD[3:0], TX_EN, and TX_ER inputs. It will, how-
ever, respond to MDIO and MDC. Clearing this bit
allows normal operation.
相關(guān)PDF資料
PDF描述
CY8CLED04DOCD1-56LTXI IC POWERPSOC DEBUG 4CH 1A 56VQFN
CYG2217 IC MOD PHONE LINE WIRE 1.07" PCB
DAC312ER IC DAC 12BIT MULT HS 20-CDIP
DAC8143FPZ IC DAC 12BIT DAISYCHAIN 16DIP
DAC8228FSZ IC DAC 8BIT DUAL V-OUT 20SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel