6.17 Loopback, Bypass, and Receiver Error Mask Register - Address 18h 15" />
參數(shù)資料
型號(hào)： CS8952-IQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 51/81頁(yè)
文件大?。?/td> 0K
描述： IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝： 90
類型： 收發(fā)器
規(guī)程： MII
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱： 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
55
DS206F1
6.17
Loopback, Bypass, and Receiver Error Mask Register - Address 18h
15
14
13
12
11
10
9
8
Bad SSD
Enable
Bypass 4B5B
Bypass
Scrambler
Bypass
Symbol
Alignment
ENDEC
Loopback
FX Drive
Remote
Loopback
PMD
Loopback
7
654
32
10
Strip Preamble
Alternate FDX
CRS
Loopback
Transmit
Disable
Code Error
Report Select
Premature End
Error Report
Select
Link Error
Report Enable
Packet Error
Report Enable
Code Error
Report Enable
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Bad SSD Enable
Read/Write 1
When set, this bit enables the reporting of a bad SSD
(False-Carrier event) on the MII. These events will be
reported by setting RX_ER=1, RX_DV=0, and
RXD[3:0]=1110.
If the 4B5B encoders are being bypassed, this event
will be reported by setting RX_DV=0 and
RXD[4:0]=11110. If symbol alignment is bypassed,
the CS8952 does not detect carrier, and thus will not
report bad SSD events.
14
Bypass 4B5B
Read/Write Reset to the value
on the BP4B5B
pin.
When set, this bit causes the receive 5B4B decoder
and the transmit 4B5B encoder to be bypassed.
13
Bypass Scrambler
Read/Write Reset to the value
on the BPSCR
pin.
When set, this bit causes the receive descrambler
and the transmit scrambler blocks to be bypassed,
and the CS8952 accepts NRZI data from an external
100BASE-FX optical module through pins RX_NRZ+
and RX_NRZ-.
12
Bypass Symbol
Alignment
Read/Write Reset to the value
on the BPALIGN
pin.
When set, this bit causes the following functions to
be bypassed: receiver descrambling, symbol align-
ment and decoding, transmit symbol encoding, and
transmit scrambling.
11
ENDEC Loopback
Read/Write 0
When set, the 10BASE-T internal Manchester
encoder output is connected to the decoder input.
When clear, the CS8952 is configured for normal
operation.
10
FX Drive
Read/Write 0
This bit controls the drive strength of the 100BASE-
FX PECL interface drivers. When clear, the drivers
are optimized for a 50
load. When set, the drivers
are optimized for a 150
load.
9
Remote Loopback
Read/Write 0
When set, data received from the link is looped back
at the MII and sent back out to the link. Received
data will be presented on the MII pins. Transmit data
at the MII will be ignored.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel
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