6.9 Interrupt Mask Register - Address 10h This register indicates which " />
參數(shù)資料
型號： CS8952-IQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 36/81頁
文件大小： 0K
描述： IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝： 90
類型： 收發(fā)器
規(guī)程： MII
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 759 (CN2011-ZH PDF)
其它名稱： 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
41
DS206F1
6.9
Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When
clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
15
14
13
12
11
10
9
8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
Premature End
Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7
654
32
10
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
CIM Link Unstable
Read/Write 0
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14
Link Status Change Read Write 1
When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
13
Descrambler Lock
Change
Read/Write 0
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
12
Premature End
Error
Read/Write 0
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
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參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel
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