6.10 Interrupt Status Register - Address 11h This register indicates whi" />
參數(shù)資料
型號(hào)： CS8952-IQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 39/81頁(yè)
文件大小： 0K
描述： IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝： 90
類型： 收發(fā)器
規(guī)程： MII
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱： 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
44
DS206F1
6.10
Interrupt Status Register - Address 11h
This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self-
clearing, and will thus be cleared upon readout.
15
14
13
12
11
10
9
8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
Premature End
Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7
654
32
10
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
CIM Link Unstable
Read Only
0
When set, this bit indicates that an unstable link con-
dition was detected by the Carrier Integrity Monitor
function.
14
Link Status Change Read Only
0
When set, this bit indicates that a change has
occurred to the status of the link. The Self Status
Register (address 19h) may be read to determine the
current status of the link.
13
Descrambler Lock
Change
Read Only
0
When set, this bit indicates that a change has
occurred in the status of the descrambler. The Self
Status Register (address 19h) may be read to deter-
mine the current status of the scrambler lock.
12
Premature End
Error
Read Only
0
This bit is set when a premature end of frame is
detected for 100 Mb/s operation. A premature end is
defined as two consecutive IDLE patterns detected in
a frame prior to the End of Stream Delimiter.
11
DCR Rollover
Read Only
0
This bit is set when the MSB of the Disconnect Count
Register (address 12h) becomes set. This should
provide ample warning to the management layer so
that the DCR may be read before rolling over.
10
FCCR Rollover
Read Only
0
This bit is set when the MSB of the False Carrier
Count Register (address 13h) becomes set. This
should provide ample warning to the management
layer so that the FCCR may be read before saturat-
ing.
9
RECR Rollover
Read Only
0
This bit is set when the MSB of the Receive Error
Count Register (address 15h) becomes set. This
should provide ample warning to the management
layer so that the RECR may be read before rolling
over.
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參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel
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