參數(shù)資料
型號(hào)： CS8952-IQZ
廠(chǎng)商： Cirrus Logic Inc
文件頁(yè)數(shù)： 52/81頁(yè)
文件大?。?/td> 0K
描述： IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝： 90
類(lèi)型： 收發(fā)器
規(guī)程： MII
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱(chēng)： 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
56
DS206F1
8
PMD Loopback
Read/Write 0
When set, the scrambled NRZI transmit data is con-
nected directly to the NRZI receive port on the
descrambler. The loopback includes all of the
100BASE-TX functionality except for the MLT-3
encoding/decoding and the analog line-interface
blocks. When clear, the CS8952 is configured for
normal operation.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
7
Strip Preamble
Read/Write 0
When set this bit causes the 7 bytes of MAC pream-
ble to be stripped off of incoming 100 Mb/s frames.
The data received across the MII will begin with the 1
byte Start of Frame Delimiter (SFD).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
6
Alternate FDX CRS Read/Write 0
This bit changes the behavior of the CRS pin only in
the full-duplex (FDX) mode of operation. When set,
CRS will be asserted for transmit data only. When
clear, CRS will be asserted only for receive data.
5
Loopback Transmit
Disable
Read/Write 1
This bit controls whether loopback data is transmitted
onto the network. When set, any data transmitted
during PMD or ENDEC loopback mode will NOT be
transmitted onto the network. When clear, data will
be transmitted on the TX+/- pins as well as looped
back onto the MII pins.
4
Code Error Report
Select
Read/Write 0
When set, this bit causes code errors to be reported
by a value of 5h on RXD[3:0] and the assertion of
RX_ER.
When clear, this bit causes code errors to be
reported by a value of 6h on RXD[3:0] and the asser-
tion of RX_ER.
This bit is superseded by the Code Error Report
Enable bit.
3
Premature End
Error Report Select
Read/Write 0
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
BIT
NAME
TYPE
RESET
DESCRIPTION
相關(guān)PDF資料
PDF描述
CY8CLED04DOCD1-56LTXI IC POWERPSOC DEBUG 4CH 1A 56VQFN
CYG2217 IC MOD PHONE LINE WIRE 1.07" PCB
DAC312ER IC DAC 12BIT MULT HS 20-CDIP
DAC8143FPZ IC DAC 12BIT DAISYCHAIN 16DIP
DAC8228FSZ IC DAC 8BIT DUAL V-OUT 20SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*