參數(shù)資料
型號: DS3160
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 11/107頁
文件大?。?/td> 592K
代理商: DS3160
DS3160
11 of 107
Table 2.1B. SIGNAL DESCRIPTION/PIN LIST (PRELIMINARY PIN
ASSIGNMENT, SORTED BY PIN NUMBER)
PIN
SYMBOL
TYPE
FUNCTION
1, 11, 18, 19, 24,
25, 88, 100
2
3
4, 5, 14, 22, 23, 31,
32, 90
6
7
8
9
10
12
13
15
16
17
20
21
26
27
28
29
30
33
34
35
36
37
38, 52, 75, 86
39
40
41
42
43
44
45
46
47
48, 60, 66, 79
49
50
51
53
54
55
56
AVDD
Positive Supply, 3.3V (±5%)
Rx+
Rx-
I
I
Receive Positive or NRZ Data Input
Receive Negative Data Input
AVSS
Ground
LPOSO
LNEGO
LCLKO
TESTIO1
TESTIO2
RxMON+
RxMON-
LPOSI
LNEGI
LCLKI
Tx+
Tx-
O
O
O
I/O
I/O
O
O
I
I
I
O
O
I
I
I
O
O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LIU POS Factory Test Signal
LIU NEG Factory Test Signal
LIU CLK Factory Test Signal
Factory Test I/O 1
Factory Test I/O 2
Receive-Monitor Positive-Data Output
Receive-Monitor Negative-Data Output
LIU POS Factory Test Signal
LIU NEG Factory Test Signal
LIU CLK Factory Test Signal
Transmit Positive or NRZ Data Output
Transmit Negative Data Output
Reset
Factory Test Input
Tri-State Output Pins Enable
Transmit-Monitor Positive-Data Output
Transmit-Monitor Negative-Data Output
JTAG IEEE 1149.1 Test Reset
JTAG IEEE 1149.1 Test Mode Select
JTAG IEEE 1149.1 Test Serial Data Output
JTAG IEEE 1149.1 Test Serial Data Input
JTAG IEEE 1149.1 Test Serial Clock
Positive Supply, 3.3V (±5%)
CPU Bus Address Latch Enable
CPU Bus Address Bit 0, LSB
CPU Bus Address Bit 1
CPU Bus Address Bit 2
CPU Bus Address Bit 3
CPU Bus Address Bit 4
CPU Bus Address Bit 5
CPU Bus Address Bit 6
CPU Bus Address Bit 7, MSB
Ground
CPU Bus Data Bit 0, LSB
CPU Bus Data Bit 1
CPU Bus Data Bit 2
CPU Bus Data Bit 3
CPU Bus Data Bit 4
CPU Bus Data Bit 5
CPU Bus Data Bit 6
RST
TEST
HIZ
TxMON+
TxMON-
JTRST
JTMS
JTDO
JTDI
JTCLK
DVDD
CALE
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
DVSS
CD0
CD1
CD2
CD3
CD4
CD5
CD6
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