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參數資料
| 型號： | DS3160 |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 90/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
90 of 107
9.3 Instruction Register and Instructions
The instruction register contains a shift register as well as a latched-parallel output, and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI
and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage
toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with
JTMS high moves the controller to the Update-IR state. The falling edge of that same JTCLK latches the
data in the instruction shift register to the instruction parallel output. Instructions supported by the
DS3160 and their respective operational binary codes are shown in Table 9.3A.
Table 9.3A. INSTRUCTION CODES
INSTRUCTION
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGH-Z
IDCODE
SELECTED REGISTER
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
INSTRUCTION CODES
010
111
000
011
100
001
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification. This instruction
supports two functions. The digital I/Os of the DS3160 can be sampled at the boundary scan register
without interfering with the normal operation of the device by using the Capture-DR state.
SAMPLE/PRELOAD also allows the DS3160 to shift data into the boundary scan register through JTDI
using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS3160. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled by the Update-IR state, the parallel
outputs of all digital output pins are driven. The boundary scan register is connected between JTDI and
JTDO. The Capture-DR samples all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising
edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification
code out serially through JTDO. During Test-Logic-Reset, the identification code is forced into the
instruction register’s parallel output. The device ID code always has a 1 in the LSB position. The next 11
bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for
the device and 4 bits for the version. The device ID code for the DS3160 is 0000D143h
.
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| DS3161 | 功能描述:網絡控制器與處理器 IC Sgl ATM/Packet PHYs for DS3/E3/STS-1 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS31612 | 制造商:Maxim Integrated Products 功能描述:12 PORT ATM/PHY 676-TEPBGA - Trays |
| DS31612N | 制造商:Maxim Integrated Products 功能描述:12 PORT ATM/PHY 676-TEPBGA IND - Trays |
| DS3161N | 功能描述:網絡控制器與處理器 IC Sgl ATM/Packet PHYs for DS3/E3/STS-1 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3162 | 功能描述:網絡控制器與處理器 IC Dual ATM/Packet PHYs for DS3/E3/STS-1 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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