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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 71/107頁 |
| 文件大小： | 592K |
| 代理商： | DS3160 |
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DS3160
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7. HDLC CONTROLLER
7.1 General Description
The DS3160 contains an on-board HDLC controller with 256-byte buffers in the transmit and receive
paths.
Receive Operation
On reset, the receive HDLC controller flushes the receive FIFO and begins searching for a new incoming
HDLC packet. The receive HDLC controller performs a bit by bit search for an HDLC packet and when
one is detected, it zero destuffs the incoming data stream and automatically byte aligns to it and places the
incoming bytes as they are received into the receive FIFO. The first byte of each packet is marked in the
receive FIFO by setting the opening byte (OBYTE) bit. Upon detecting a closing flag, the device checks
the 16-bit CRC to see if the packet is valid or not and then marks the last byte of the packet in the receive
FIFO by setting the closing byte (CBYTE) bit. The CRC is not passed to the receive FIFO. When the
CBYTE is set, the host can obtain the status of the incoming packet through the packet status bits (PS0
and PS1). Incoming packets can be separated by a single flag or even by two flags that share a common 0.
If the receive FIFO ever fills beyond capacity, the new incoming packet data is discarded and the receive
FIFO overrun (ROVR) status bit is set. If such a scenario occurs, then the last packet in the FIFO is
suspect and should be discarded. When an overflow occurs, the receive HDLC stops accepting packets
until either the FIFO is completely emptied or reset. If the receive HDLC controller ever detects an
incoming abort (seven or more 1’s in a row), it sets the receive-abort-sequence-detected (RABT) status
bit. If an abort sequence is detected in the middle of an incoming packet, then the receive HDLC
controller sets the packet status bits accordingly.
The receive HDLC has been designed to minimize its real-time host-support requirements. The receive
FIFO is 256 bytes, which is deep. The host is notified when a new message has begun (receive-packet-
start status bit) to be received and when a packet has completed (receive-packet-end status bit). Also the
host can be notified when the FIFO has filled beyond a programmable level called the high watermark.
The host reads the incoming packet data out of the receive FIFO a byte at a time. When the receive FIFO
is empty, the REMPTY bit in the FIFO is set.
Transmit Operation
On reset, the transmit HDLC controller flushes the transmit FIFO and transmits an abort followed by
either 7Eh or FFh (depending on the setting of the TFS control bit) continuously. The transmit HDLC
then waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC automatically adds an opening flag of 7Eh to the beginning of the packet and zero stuffs
the outgoing data stream. When the transmit HDLC controller detects that the TMEND bit in the transmit
FIFO is set, it automatically calculates and adds in the 16-bit CRC checksum, followed by a closing flag
of 7Eh. If the FIFO is empty, then it begins sending either 7Eh or FFh continuously. If there is some more
data in the FIFO, then the transmit HDLC automatically adds in the opening flag and sends the next
packet. Between consecutive packets there is always at least two flags of 7Eh. If the transmit FIFO ever
empties when a packet is being sent (i.e., before the TMEND bit is set), then the transmit HDLC
controller sends an abort of seven 1’s in a row (FEh), followed by a continuous transmission of either 7Eh
(flags) or FFh (idle), and the transmit-FIFO-underrun (TUDR) status bit is set. When the FIFO underruns,
the transmit HDLC controller should be reset by the host.
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