參數(shù)資料
型號: DS3160
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 91/107頁
文件大?。?/td> 592K
代理商: DS3160
DS3160
91 of 107
HIGH-Z
All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO.
CLAMP
All digital outputs output data from the boundary scan parallel output while connecting the bypass register
between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
9.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan
register. An optional test register has been included in the DS3160 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGH-Z
instructions and provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched-parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Boundary Scan Register
This register contains both a shift register path and a latched-parallel output for all control cells and
digital I/O cells and is 196 bits in length. Table 9.4A lists all cell bit locations and definitions.
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