參數(shù)資料
型號(hào): DS3160
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 46/107頁(yè)
文件大小: 592K
代理商: DS3160
DS3160
46 of 107
Figure 5.2D. FRDEN AND FTDEN 1.5Mbps TIMING
Bit 5/Transmit Remote Alarm Indication (TRAI).
When this bit is set high, the RAI pattern is sent on
the M-bit.
0 = do not transmit RAI
1 = transmit RAI
Bit 6/Automatic Transmit Remote Alarm Indication on LOS (TRAILOS).
When this bit is set high,
the RAI pattern is sent on the M-bit automatically when the framer declares a loss-of-signal (LOS)
occurrence. Transmission of RAI terminates when LOS is cleared.
0 = disable automatic RAI transmit
1 = enable automatic RAI transmit
Bit 7/Automatic Transmit Remote Alarm Indication on LOF (TRAILOF).
When this bit is set high,
the RAI pattern is sent on the M-bit automatically when the framer declares a loss-of-frame (LOF)
occurrence. Transmission of RAI terminates when LOF is cleared.
0 = disable automatic RAI transmit
1 = enable automatic RAI transmit
Bits 8/Frame Error-Counting Control Bit (FECC).
This bit is used to control what events are counted
by the frame error counter. When this bit is set low, the counter accumulates LOF occurrences. When this
bit is set high, the counter accumulates F-bit errors.
Bit 9/Error-Counting Control (ECC).
This bit is used to control whether the device increments the
error counters during LOF conditions. It affects the frame error counter only when it is configured to
count frame errors, not LOF occurrences. When this bit is set low, the frame error counter and CRC error
counter are not allowed to increment during LOF conditions. When this bit is set high, both counters are
allowed to increment during LOF conditions.
0 = stop the FECR and CRCCR error counters from incrementing during LOF
1 = allow the FECR and CRCCR error counters to increment during LOF
Bit #
Frame 1
Frame 2
Frame 3
Frame 4
1–8
193–
200
TS1
TS1
TS1
TS1
TS25
TS24
761–
768
769–
776
777–
784
785
786
787
788
789
TS97 TS98
TS96
TS97 TS98
TS96
TS97 TS98
TS96
TS97 TS98
TS96
1
1
0
0
m
1
0
1
0
0
x1`
x2
x3
a
m
e1
e2
e3
e4
e5
FRDEN/
FTDEN
TS24
TS24
TS24
185–
192
TS25
TS25
TS25
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