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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 30/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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4.2 Master Configuration Registers Description
Register Name:
Register Description:
Register Address:
MC1
Master Configuration Register 1
02h
Bit #
Name
Default
7
6
5
4
3
2
1
0
LLB
0
DLB
0
DENMS
0
TAIS
0
LOTCMC
0
MECU
0
AECU
0
ZCSD
0
Bit #
Name
Default
15
14
N/A
0
13
ALB
0
12
11
10
9
8
FRDAIS
1
JASEL
0
JAEN
0
RMONEN
0
TMONEN
0
TDRVEN
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Zero Code Suppression Disable (ZCSD)
0 = enable the B8ZS
1 = disable the B8ZS
Bit 1/Automatic One-Second Error Counters Update Defeat (AECU).
When this bit is set low, the
device automatically updates the performance error counters on an internally created 1-second boundary.
The host is notified of the update by the setting of the OST status bit in the master status register. In this
mode, the host has a full 1-second period to retrieve the error information before it is overwritten with the
next update. When this bit is set high, the device defeats the automatic 1-second update and enables a
manual update mode. In the manual update mode, the device relies on either the framer manual error-
counter update (FRMECU) hardware-input signal or the MECU control bit to update the error counters.
The FRMECU hardware input signal and MECU control bit are logically OR’ed and hence a 0-to-1
transition on either initiates an error-counter update to occur. After either the FRMECU signal or MECU
bit has toggled, the host must wait at least 100ns before reading the error counters to allow the device
time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
Bit 2/Manual Error-Counter Update (MECU).
A 0-to-1 transition on this bit causes the device to
update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit
must be cleared and set again for a subsequent update. This bit is logically OR’ed with the external
FRMECU hardware input signal. After this bit has toggled, the host must wait at least 100ns before
reading the error counters to allow the device time to complete the update.
Bit 3/Loss-of-Transmit Clock Mux Control (LOTCMC).
The DS3160 can detect if the FTCLK fails to
transition. If this bit is set low, the device takes no action (other than setting the LOTC status bit) when
the FTCLK fails to transition. When this bit is set high, the device automatically switches to the internal
receive clock (RCLK) when the FTCLK fails and transmit AIS.
0 = do not switch to the RCLK signal if FTCLK fails to transition
1 = automatically switch to the RCLK signal if the FTCLK fails to transition and send AIS
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