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參數(shù)資料
| 型號(hào)： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 15/107頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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2.2 CPU Bus Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal should be connected low when the device is to be operated as a 16-bit bus. This signal should
be connected high when the device is to be operated as an 8-bit bus.
0 = CPU bus is in the 16-bit mode
1 = CPU bus is in the 8-bit mode
CMS
CPU Bus Mode Select
Input
Signal Name:
Signal Description:
Signal Type:
The signal determines whether the CPU bus operates in the Intel mode (CIM = 0) or the Motorola mode
(CIM = 1). The signal names in parenthesis are operational when the device is in the Motorola mode.
0 = CPU bus is in the Intel mode
1 = CPU bus is in the Motorola mode
CIM
CPU Bus Intel/Motorola Bus Select
Input
Signal Name:
Signal Description:
Signal Type:
The external host configures the device and obtains real-time status information about the device through
these signals. When reading data from the CPU bus, these signals are outputs. When writing data to the
CPU bus, these signals become inputs. When the CPU bus is operated in the 8-bit mode (CMS = 1), CD8
to CD15 are inactive and should be connected low.
CD0 to CD15
CPU Bus Data Bus
Input/Output (Tri-State Capable)
Signal Name:
Signal Description:
Signal Type:
These input signals determine which internal device configuration register that the external host wishes to
access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be
connected low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant
address bit.
CA0 to CA7
CPU Bus Address Bus
Input
Signal Name:
Signal Description:
Signal Type:
In Intel mode (CIM = 0), this signal determines when data is to be written to the device. In Motorola
mode (CIM = 1), this signal is used to determine whether a read or write is to occur.
CWR
(CR
/W
)
CPU Bus Write Enable (CPU Bus Read/Write Select)
Input
Signal Name:
Signal Description:
Signal Type:
In Intel mode (CIM = 0), this signal determines when data is to be read from the device. In Motorola
mode (CIM = 1), a rising edge is used to write data into the device.
CRD
(
CDS
)
CPU Bus Read Enable (CPU Bus Data Strobe)
Input
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| DS3161N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Sgl ATM/Packet PHYs for DS3/E3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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