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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 20/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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2.4 Transmit Formatter Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal can be configured to be either an input or output. When FTSOF is an input (default state), a
1-to-0 transition sets the first framing bit in each frame or multiframe. When FTSOF is an input, a pulse is
not required at every frame or multiframe boundary. The FTSOF as an input must not be less than a frame
cycle of 125μs, or must be configured as an output. When this signal is an output, it pulses for one
FTCLK period to indicate frame or multiframe boundary. When configured as an output and in the frame
mode, FTSOF pulses high for one out of every 789 clock cycles, providing a frame reference. When
configured as an output and in the multiframe mode, FTSOF pulses high for one out of every 3156 clock
cycles, providing a multiframe reference. This signal can be configured to be either active high (normal
mode) or active low (inverted mode) (Figure 2.4B).
FTSOF
Transmit Formatter Start-of-Frame Sync Signal
Output/Input (with internal 10k
pullup)
Signal Name:
Signal Description:
Signal Type:
An accurate 6.312MHz 30ppm clock should be applied at this signal. This signal is used to clock data
into the transmit formatter. Transmit data can be clocked into the device either on a rising edge (normal
mode) or a falling edge (inverted mode).
FTCLK
Transmit Formatter Clock
Input
Signal Name:
Signal Description:
Signal Type:
This signal inputs data into the transmit formatter. This signal can be sampled either on the rising edge of
FTCLK (normal mode) or the falling edge of FTCLK (inverted mode). In addition, the data input to this
signal can be internally inverted.
FTD
Transmit Formatter Serial Data
Input
Signal Name:
Signal Description:
Signal Type:
This signal can be configured to either output a data enable or a gapped clock and use FTSOF for an
alignment reference or ignore FTSOF (free-running option, see ALTFTDEN in MC2). When using
FTSOF as a reference and in the data enable mode, this signal goes active when data should be made
available at the FTD input. When using FTSOF as a reference and in the gapped clock mode, this signal
acts as a demand clock for the FTD input and it transitions for each bit of data needed at the FTD input
and it is suppressed when the transmit formatter inserts overhead data and, therefore, no data is needed at
the FTD input. When the free-running mode is enabled, there is no correlation of FTDEN and when data
is made available at FTD. This signal can be internally inverted (Figure 2.4A).
FTDEN
Transmit Formatter
Serial Data-Enable or Gapped Clock Output
Output
Signal Name:
Signal Description:
Signal Type:
The DS3160 can be configured to use this asynchronous input to cause errors to be inserted into the
transmitted data stream. A 0-to-1 transition on this input causes the device to begin the process of causing
errors to be inserted. This signal must be returned low before any subsequent errors can be generated. If
this signal is not used, then it should be connected low.
FTMEI
Transmit Formatter Manual Error Insert Strobe
Input
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