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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 17/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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2.3 Receive Framer Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal pulses for one FRCLK period to indicate a frame or multiframe boundary. When configured in
the frame mode, FRSOF indicates the position of the first bit (bit position 1) in each J2 frame. When
configured in the multiframe mode, FRSOF indicates the position of the first bit (bit position 1) in each J2
multiframe. This signal can be configured to be either active high (normal mode) or active low (inverted
mode). See Figure 2.3B.
FRSOF
Receive Framer Start-of-Frame Sync Signal
Output
Signal Name:
Signal Description:
Signal Type:
This signal outputs the clock that is used to pass data through the receive framer. It can be sourced from
either the recovered receive clock, MCLK, or FTCLK inputs. During an LIU loss of signal (LIULOS = 1),
the clock applied at MCLK (or FTCLK if MCLK is connected high) appears at this signal. This signal is
used to clock the receive data out of the device at the FRD output. Data can be either updated on a rising
edge (normal mode) or a falling edge (inverted mode).
FRCLK
Receive Framer Clock
Output
Signal Name:
Signal Description:
Signal Type:
This signal outputs data from the receive framer. This signal is updated either on the rising edge of
FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). In addition, this signal can be
internally inverted. FRD is forced to all 1’s during a LOS and/or LOF condition.
FRD
Receive Framer Serial Data
Output
Signal Name:
Signal Description:
Signal Type:
This signal can be configured to either output a data enable or a gapped clock. In the data-enable mode,
this signal goes active when enabled timeslots are available at the FRD output and is inactive when
disabled timeslots or F-bits are being output at the FRD output. In the gapped clock mode, this signal
transitions for each bit contained in enabled timeslots and is suppressed for each bit of disabled timeslots
and the F-bits. This signal can be internally inverted (Figure 2.3A).
FRDEN
Receive Framer Serial Data-Enable or Gapped Clock Output
Output
Signal Name:
Signal Description:
Signal Type:
The DS3160 can be configured to use this asynchronous input to initiate an updating of the internal error
counters. A 0-to-1 transition on this input causes the device to begin loading the internal error counters
with the latest error counts. This signal must be returned low before a subsequent updating of the error
counters can occur. The host must wait at least 100ns before reading the error counters to allow the device
time to update the error counters.
FRMECU
Receive Framer Manual Error-Counter Update Strobe
Input
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