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參數(shù)資料
| 型號(hào)： | DS3160 |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 63/107頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
63 of 107
Register Name:
Register Description:
Register Address:
BERTC0
BERT Control Register 0
22h
Bit #
Name
Default
7
6
5
4
3
2
1
0
N/A
0
TINV
0
RINV
0
PS2
0
PS1
0
PS0
0
LC
0
RESYNC
0
Bit #
Name
Default
15
14
13
12
N/A
0
11
10
9
8
IESYNC
0
IEBED
0
IEOF
0
RPL3
0
RPL2
0
RPL1
0
RPL0
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Force Resynchronization (RESYNC).
A low-to-high transition forces the receive BERT
synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high
whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a
subsequent resynchronization.
Bit 1/Load Bit and Error Counters (LC).
A low-to-high transition latches the current bit and error
counts into the host accessible registers BERTBC0, BERTBC1 (bit count) and BERTEC0, BERTEC1
(error count), and clears the internal count. This bit should be toggled from low to high whenever the host
wishes to begin a new read-acquisition period. Must be cleared and set again for a subsequent loads.
Bit 2/Pattern Select Bit 0 (PS0), Bit 3/Pattern Select Bit 0 (PS1), Bit 4/Pattern Select Bit 1 (PS2)
000 = Pseudorandom Pattern 2
7
- 1 (ANSI T1.403-1999 Annex B)
001 = Pseudorandom Pattern 2
11
- 1 (ITU O.153)
010 = Pseudorandom Pattern 2
15
- 1 (ITU O.151)
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a 1 forced if the next 14 positions are 0)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
Bit 5/Receive Invert Data-Enable (RINV)
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6/Transmit Invert Data-Enable (TINV)
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
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