參數(shù)資料
型號(hào)： DS3160
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 82/107頁(yè)
文件大?。?/td> 592K
代理商： DS3160
DS3160
82 of 107
8. LINE INTERFACE UNIT
The line interface unit (LIU) performs all of the functions necessary for interfacing at the physical layer
lines. The device has independent receive and transmit paths (Figure 1B). The receiver performs clock
and data recovery and monitors for the loss of the incoming signal. The transmitter accepts data from the
formatter and creates the waveforms that are driven onto the coaxial (coax) cable.
Receiver
The DS3160 interfaces to the receive coax line by a 1:1 transformer (Figure 8A). The receiver
automatically adapts to coax cable losses from 0 to 15dB, which translates into 0 to 380m of coax cable
(AT&T 734A or equivalent). The receiver has excellent jitter tolerance characteristics.
The receiver contains an analog LOS detector, which resides in the equalizer. If the incoming signal drops
below -18dB (typ) of the nominal signal level, the analog LOS detector activates and it squelches the
recovered data and forces all 0’s out of the data recovery circuitry. The analog LOS detector does not
clear until the signal level is above -14dB (typ) of the nominal signal level. While the device is in a loss of
signal state, the RCLK output is referenced to the MCLK input.
Tx+ and Tx- Transmitter
The clock applied at the FTCLK input is used to transmit data out onto the JT2 line. Hence, FTCLK must
be of transmission quality (i.e., accurate to 30ppm). The duty cycle of FTCLK is not a key parameter as
long as the clock high and low times listed in Section 11 are met.
The DS3160 interfaces to the transmit JT2 coax cable by a 1:1 transformer (Table 8A and Figure 8C). It
drives the 75
cable and creates the proper waveforms required for interfacing to JT2 lines. The
transmitter can be disabled and the Tx+ and Tx- outputs tri-stated by the master configuration register
(MC1). See Section 4 for details.
Jitter Attenuator
The DS3160 contains an on-board jitter attenuator that can be placed in either the receive path or the
transmit path or disabled. Options are selected through the master configuration register (MC1). See
Section 4.2 in this data sheet for selection details and register bit settings.
The jitter attenuator consists of a narrowband PLL to retime the LIU master clock (MCLK), a 16 x 2-bit
FIFO to buffer the associated data while the clock is being retimed, and logic to prevent over/underflow
of the FIFO in the presence of very large jitter amplitudes. The PLL requires a stable, accurate clock on
MCLK. It has a loop bandwidth of 98.1Hz, and attenuates jitter at frequencies higher than the loop
bandwidth while allowing jitter (and wander) at lower frequencies to pass through relatively unaffected.
Figure 8B shows an example of jitter attenuation versus frequency.
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