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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 49/107頁 |
| 文件大小： | 592K |
| 代理商： | DS3160 |
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DS3160
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Bit 4/CRC Error Insert (CRCI).
A 0-to-1 transition on this bit causes the transmit formatter to generate
a CRC-5 error. Once this bit has been toggled from a 0 to a 1, the device waits for the next possible CRC-
5 word to insert the error. This bit must be cleared and set again for a subsequent error to be inserted. In
the manual-error-insert mode (MEIMS = 1), errors are inserted on each toggle of the FTMEI input signal
as long as this bit is set high. When this bit is set low, no errors are inserted. Only CRC-5 bits are
corrupted by this function.
Bit 5/Manual-Error-Insert Mode Select (MEIMS).
When this bit is set low, the device inserts errors on
each 0-to-1 transition of the BPVI, EXZI, or FBEI control bits. When this bit is set high, the device inserts
errors on each 0-to-1 transition of the FTMEI input signal. The appropriate BPVI, EXZI, or FBEI control
bit must be set to 1 for this to occur. If all of the BPVI, EXZI, and FBEI control bits are set to 0, no errors
are inserted.
0 = use 0-to-1 transition on the BPVI, EXZI, or FBEI control bits to insert errors
1 = use a 0-to-1 transition on the FTMEI input signal to insert errors
Bit 6/Alternate AIS Enable (ALTAIS).
When set low, the device determines AIS using the default
criteria. When set high, the device determines AIS using the alternate criteria. See Table 5.3A,
Alarm
Criteria
, for additional details.
ALTAIS
SET CRITERIA
CLEAR CRITERIA
Three or more 0’s among the four
frames received
Two or more 0’s among 96 frames
(75,744 bits) received
0
Two or fewer 0’s among the four
frames received
One or fewer 0’s among 96 frames
(75,744 bits) received
1
Bit 8/Remote-End Alarm Bit (A).
When set low, the device inserts a 0 in the A-bit position (bit 788 of
the third frame in the multiframe). When set high, the device inserts a 1 in the A-bit position.
0 = set the A-bit to 0
1 = set the A-bit to 1
Bits 9, 10, 11/Spare Bits (X1, X2, X3).
These control register bits determine what values are loaded into
the spare bit locations (bits 785, 786, 787) of the third frame in the multiframe. X1 maps into bit 785; X2
maps into bit 786; X3 maps into bit 787. These bits should be set to a 1 if not used.
0 = set the X-bit to 0
1 = set the X-bit to 1
Bit 12/Remote-End Alarm-Detected Threshold (RALMTH).
This bit selects the number of
consecutive A-bits required to set and clear the remote-end alarm-detected status bit found in SR1.
0 = alarm set when the A-bit has been a logic 1 for three consecutive frames and reset when the A-bit
has been a logic 0 for three consecutive frames
1 = alarm set when the A-bit has been a logic 1 for five consecutive frames and reset when the A-bit
has been a logic 0 for five consecutive frames
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