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| 型號： | EWIXP455ABT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁數(shù)： | 117/163頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | EWIXP455ABT |
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Package Information
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
57
Document Number: 306261-002
Table 14.
High-Speed, Serial Interface 1 (Sheet 1 of 2)
Name
Power
on
Reset
Normal
After
Reset
Until
Software
Enables
Normal
After
Software
Enables
Type
Description
HSS_TXFRAME1
Z
VB
I/O
The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to
allow an external source to be synchronized with the transmitted data. Often known as a Frame
Sync signal. Configured as an input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel IXP45X and Intel IXP46X Product
Line of Network Processors Developer’s Manual)
and is not being used in a system design, this
interface/signal is not required for any connection.
HSS_TXDATA1
Z
VOD
OD
Transmit data out. Open Drain output.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor to VCCP. When this interface is disabled via the
HSS soft fuse (refer to Expansion Bus Controller chapter of the Intel IXP45X and Intel IXP46X
Product Line of Network Processors Developer’s Manual)
and is not being used in a system
design, this interface/signal is not required for any connection.
HSS_TXCLK1
Z
VB
I/O
The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output.
The clock can be a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the
transmitted data. Configured as an input upon reset. Frame sync and Data can be selected to be
generated on the rising or falling edge of the transmit clock.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor.
HSS_RXFRAME1
Z
VB
I/O
The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to
allow an external source to be synchronized with the received data. Often known as a Frame Sync
signal. Configured as an input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel IXP45X and Intel IXP46X Product
Line of Network Processors Developer’s Manual)
and is not being used in a system design, this
interface/signal is not required for any connection.
NOTE:
This table discusses all features supported on the Intel IXP45X and Intel IXP46X Product Line of Network Processors. For details on feature support listed by processor,
For a legend of the Type codes, see Table 10 on page 46.
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