參數(shù)資料
型號： EWIXP455ABT
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 266 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 70/163頁
文件大?。?/td> 1123K
代理商： EWIXP455ABT
Electrical Specifications
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
161
5.6.3
Reset Timings
Figure 48.
Reset Timings
Table 81.
Reset Timings Table Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
Note
TRELEASE_PWON_RST_N
Minimum time required to hold the PWON_RST_N at logic
0 state after stable power has been applied to the IXP45X/
IXP46X network processors.
500
ms
TRELEASE_RESET_IN_N
Minimum time required to hold the RESET_IN_N at logic 0
state after PWON_RST_N has been released to a logic 1
state. The RESET_IN_N signal must be held low when the
PWON_RST_N signal is held low.
10
ns
TPLL_LOCK
Maximum time for PLL_LOCK signal to drive to logic 1 after
RESET_IN_N is driven to logic 1 state. The boot sequence
does not occur until this period is complete.
10
s
TEX_ADDR_SETUP
Minimum time for the EX_ADDR signals to drive the inputs
prior to RESET_IN_N being driven to logic 1 state. This is
used for sampling configuration information.
50
ns
TEX_ADDR_HOLD
Minimum/maximum time for the EX_ADDR signals to drive
the inputs prior to PLL_LOCK being driven to logic 1 state.
This is used for sampling configuration information.
020
ns
TWARM_RESET
Minimum time required to drive RESET_IN_N signal to
logic 0 in order to cause a reset after the IXP45X/IXP46X
network processors have been in normal operation. The
power must remain stable and the PWON_RST_N signal
must remain stable.
500
ns
NOTES:
1. TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability. When an external oscillator is being
used the 500-ms delay is not required.
2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic
device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active.
VCCP
VCCM
VCC
PLL_LOCK
PWRON_RESET_N
RESET_IN_N
EX_ADDR[24:0]
EX_ADDR[24:0]-Pull Up/Down
CFG Settings To Be Captured
IXP46X Drives Outputs
TRELEASE_PWRON_RST_N
TEX_ADDR_SETUP
TRELEASE_RST_N
TPLL_LOCK
TEX_ADDR_HOLD
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