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參數(shù)資料
| 型號(hào)： | EWIXP455ABT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁(yè)數(shù)： | 82/163頁(yè) |
| 文件大小： | 1123K |
| 代理商： | EWIXP455ABT |
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Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
25
In order to limit double-bit errors from occurring, periodically reading the entire usable memory
array will allow the hardware unit within the memory controller to correct any single-bit, ECC
errors that may have occurred prior to these errors becoming double-bit ECC errors. Using this
method is system-dependent.
It is important to note as well, that when sub-word writes (byte writes or half-word writes) to a
32-bit memory with ECC enabled, the memory controller will implement read-modify writes.
Implementing read-modify writes is important to understand when understanding performance
implications when writing software.
To understand a read-modify write, understanding that a byte to be written falls within a 32-bit
word which is addressed on a word-aligned boundary. When a byte write is requested, the memory
controller will read the 32-bit word which encompasses the byte that is to be written. The memory
controller will then modify the specified byte, calculate a new ECC, and then write the entire 32-bit
word back into the memory location it was read from.
The value written back into the memory location will contain the 32-bit word with the modified
byte and the new ECC value.
The MCU supports two banks of DDR SDRAM. The MCU has support for unbuffered DDRI 266
only.
Table 4 illustrates the supported DDR SDRAM configurations for the IXP45X/IXP46X network
processors. The 128/256/512-Mbit, 1-Gbit DDRI SDRAM devices comprise four internal leaves.
The MCU controls the leaf selects within 128/256/512-Mbit, 1-Gbit DDRI SDRAM by toggling
DDRI_BA[0] and DDRI_BA[1].
The two DDR SDRAM chip enables (DDRI_CS[1:0]#) support a DDRI SDRAM memory
subsystem consisting of two banks. The base address for the two contiguous banks are
programmed in the DDR SDRAM Base Register (SDBR) and must be aligned to a 32-Mbyte
boundary. The size of each DDR SDRAM bank is programmed with the DDR SDRAM boundary
registers (SBR0 and SBR1).
Table 4.
Supported DDRI Memory Configurations (Sheet 1 of 2)
DDRI SDRAM
Technology
DDRI SDRAM
Arrangement
# Banks
Address Size
Leaf Select
Total
Memory
Size1
Page
Size2
Row
Col
DDRI_BA[1]
DDRI_BA[0]
128 Mbit
16M x 8
1
12
10
I_AD[26]
I_AD[25]
64 Mbyte
4K
2
128 Mbyte
4K
8M x 16
1
12
9
I_AD[25]
I_AD[24]
32 Mbyte
2K
2
64 Mbyte
2K
256 Mbit
32M x 8
1
13
10
I_AD[27]
I_AD[26]
128 Mbyte
4K
2
256 Mbyte
4K
16M x 16
1
13
9
I_AD[26]
I_AD[25]
64 Mbyte
2K
2
128 Mbyte
2K
NOTES:
1. Table indicates 32-bit-wide memory subsystem sizes
2. Table indicates 32-bit-wide memory page sizes
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