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參數(shù)資料
| 型號(hào)： | EWIXP455ABT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁數(shù)： | 94/163頁 |
| 文件大小： | 1123K |
| 代理商： | EWIXP455ABT |
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Functional Overview
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
36
Document Number: 306261-002
The IMMU then continues the instruction pre-fetch by using the address translation just entered
into the ITLB. When an instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch
using the address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When an
instruction pre-fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a pre-fetch abort is sent to the core for exception processing. The IMMU and
DMMU can be enabled or disabled together.
3.2.4
Data Memory Management Unit
For data fetches, the Data Memory Management Unit (DMMU) controls logical-to-physical
address translation, memory-access permissions, memory-domain identifications, and attributes
(governing operation of the data cache or mini-data cache and write buffer). The DMMU contains
a 32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-robin
replacement policy. DTLB entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism
that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor
contains information for logical-to-physical address translation, memory-access permissions,
memory-domain identifications, and attributes (governing operation of the D-cache or mini-data
cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into the DTLB.
When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation
already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a data fetch
is attempted to an area of memory in violation of access permissions, the attempt is aborted and a
data abort is sent to the core for exception processing.
The IMMU and DMMU can be enabled or disabled together.
3.2.5
Instruction Cache
The Instruction Cache (I-Cache) can contain high-use, multiple-code segments or entire programs,
allowing the core access to instructions at core frequencies. This prevents core stalls caused by
multi-cycle accesses to external memory.
The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way
contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word),
and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are
replaceable via a round-robin policy.
The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the
ITLB of the IMMU — provide some control over an enabled I-cache.
When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical
word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next
instruction to be accessed from the I-cache, but only when its data operands do not depend on the
execution results of the instruction being fetched via the queue.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EWIXP455BAC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EWIXP460BAD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
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| EWK105BJ224MPHF | 功能描述:CAP CER 0.22UF 16V X5R 0204 制造商:taiyo yuden 系列:LWDC?，LW 包裝:剪切帶（CT） 零件狀態(tài):在售 電容:0.22μF 容差:±20% 電壓 - 額定:16V 溫度系數(shù):X5R 工作溫度:-55°C ~ 85°C 特性:低 ESL 型（倒置結(jié)構(gòu)） 等級(jí):AEC-Q200 應(yīng)用:汽車，旁通，去耦 故障率:- 安裝類型:表面貼裝，MLCC 封裝/外殼:0204（0610 公制） 大小/尺寸:0.020" 長 x 0.039" 寬（0.52mm x 1.00mm） 高度 - 安裝（最大值）:- 厚度（最大值）:0.014"（0.35mm） 引線間距:- 引線形式:- 標(biāo)準(zhǔn)包裝:1 |
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