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參數(shù)資料
| 型號： | EWIXP455ABT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁數(shù)： | 122/163頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | EWIXP455ABT |
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Package Information
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
61
Document Number: 306261-002
UTP_OP_DATA[7] /
SMII_TXDATA[4]
ZZ
Z
VO
TRI
UTOPIA Mode of Operation:
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to
an ATM UTOPIA Level 2-compliant PHY.
MII Mode of Operation:
Not used.
SMII mode of operation:
Output data for SMII interface number four. The data on this signal is transmitted synchronously
with respect to the rising edge of SMII_CLK when operating as an SMII interface and
synchronously with respect to the rising edge of SMII_TXCLK when operating as a Source
Synchronous SMII interface
UTP_OP_ADDR[4:0]
Z
VO
O
Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and
select a single PHY at any given time.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual)
and is not
being used in a system design, this interface/signal is not required for any connection.
UTP_OP_FCI
Z
VI
I
UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal.
Used to inform the processor of the ability of each polled PHY to receive a complete cell. For cell-
level flow control in an MPHY environment, TxClav is an active high tri-stateable signal from the
MPHY to ATM layer. The UTP_OP_FCI, which is connected to multiple MPHY devices, will see
logic high generated by the PHY, one clock after the given PHY address is asserted — when a full
cell can be received by the PHY. The UTP_OP_FCI will see a logic low generated by the PHY one
clock cycle, after the PHY address is asserted — if a full cell cannot be received by the PHY.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual)
and is not
being used in a system design, this interface/signal is not required for any connection.
Table 15.
UTOPIA Level 2/MII_A/ SMII[4] Interface (Sheet 3 of 9)
Name
Power
on
Reset
Normal
After
Reset
Until
Software
Enables
Normal
After
Software
Enables
Type
Description
NOTE:
This table discusses all features supported on the Intel IXP45X and Intel IXP46X Product Line of Network Processors. For details on feature support listed by processor,
see Table 1 on page 14.
For a legend of the Type codes, see Table 10 on page 46.
For information on selecting the desired interface, see the Intel
IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual.
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