參數(shù)資料
型號(hào)： EWIXP455ABT
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 266 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 51/163頁
文件大小： 1123K
代理商： EWIXP455ABT
Electrical Specifications
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
144
Document Number: 306261-002
Figure 35.
Motorola* Multiplexed Mode
Table 68.
Motorola* Multiplexed Mode Values (Sheet 1 of 2)
Symbol
Parameter
Min.
Max.
Units
Notes
Talepulse
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
1
4
Cycles
1, 7
Tale2addrhold Valid address hold time after from falling edge of ALE
1
Cycles
Tdval2valds
Write data valid prior to EXP_MOT_DS_N falling edge
1
4
Cycles
3, 7
NOTES:
1. The EX_ALE signal is extended form T to 4T nnsec, based on the programming of the T1 timing parameter.
The parameter Tale2addrhold is fixed at T.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external
device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address,
and data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. T is the period of the clock measured in ns.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing was designed for a system load between 5pF and 60pF for high drive setting
A9587-01
EX_CLK
EX_ADDR
EX_DATA
EX_RD_N
(exp_mot_rnw)
EX_WR_N
(exp_mot_ds_n)
EX_DATA
EX_ALE
Valid Address
T5
1-16 Cycles
T4
1-4 Cycles
EX_CS_N
Trecov
Tale2addrhold
Tdval2valds
EX_WR_N
(exp_mot_ds_n)
EX_RD_N
(exp_mot_rnw)
Tdhold2afterds
T3
1-16 Cycles
T2
1-4 Cycles
T1
2-5 Cycles
ALE Extended
Talepulse Tale2valcs
Tdspulse
Address
Output Data
Address
Input Data
Multiplexed Address/Data
Trdsetup
Trdhold
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