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參數資料
| 型號： | EWIXP455ABT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁數： | 90/163頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | EWIXP455ABT |
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Functional Overview
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
32
Document Number: 306261-002
The EAU supports various large number arithmetic operations. These operations include modular
exponentiation, modular reduction, multiply, add and subtract. These operations are controlled
through a set of memory mapped registers. Parameters for and results of the operations are written
in little-endian ordering into a RAM (contained within the EAU) which the EAU state machine
accesses and also uses for temporary registers. The arithmetic operations supported by the EAU are
used by software executing in the host processor to build larger cryptographic functions such as
signing and verification procedures. Since the EAU executes only one operation at a time, the host
processor must serialize the required operations to the EAU.
The EAU begins operating after the host processor has moved data into the EAU RAM and loads
the EAU’s command register with an appropriate command. After executing the command, the
EAU appropriately sets its status bits and waits idle until it receives another command from the
host processor.
The RNG unit provides a digital, random-number generation capability. It uses a LFSR (Linear
Feedback Shift Register) to generate a sequence of pseudo-random bits. These sequences are
shifted into a FIFO of 32-bit words, which may be read sequentially from the random number
register. A new word is generated every 32 clocks and the RNG will buffer 16 of these words at a
time.
The output of the RNG should be passed through the SHA engine for added randomness. The host
processor (Intel XScale core) is responsible for implementing this SHA-based, random-number
generation. The LFSR also allows one entropy source. The entropy source is fed in from a PN
sequence generator which has a period of 2^42 - 1. The coefficients for the PN sequence is chosen
such that it produces the maximal sequence length. The coefficients are not mentioned for security
reasons. The coefficients for the 128-stage LSFR are similarly not mentioned here for security
reasons.
3.1.21
Queue Manager
The Queue Manager provides a means for maintaining coherency for data handling between
various processors cores contained on the IXP45X/IXP46X network processors (NPE to NPE,
NPE to Intel XScale core, etc.). It maintains the queues as circular buffers in an embedded 8-Kbyte
SRAM. The Queue Manager also implements the status flags and pointers required for each queue.
The Queue Manager manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The Queue Manager interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to
the NPE condition select logic), and two interrupts to the Intel XScale core.
The AHB interface is used for configuration of the Queue Manager and provides access to queues,
queue status, and SRAM. Individual queue status for queues 0-31 is communicated to the NPEs via
the flag bus. Combined queue status for queues 32-63 are communicated to the NPEs via the event
bus. The two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to
the Intel XScale core.
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