參數(shù)資料
型號： EWIXP455ABT
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 266 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 58/163頁
文件大?。?/td> 1123K
代理商： EWIXP455ABT
Electrical Specifications
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
150
Document Number: 306261-002
Figure 38.
HPI*-16 Multiplexed Write Mode
Table 74.
HPI*-16 Multiplexed Read Accesses Values
Symbol
Parameter
Min.
Max.
Units
Notes
Tadd_setup
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
11
45
Cycles 1, 5, 6
Tcs2hds1val
Delay from chip select being active and the HDS1 data
strobe being active.
3
4
Cycles 5, 6
Thds1_pulse
Pulse width of the HDS1 data strobe
4
5
Cycles 2, 4, 5
Tdata_setup
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
4
5
Cycles 3, 5, 6
Trecov
Time required between successive accesses on the
expansion interface.
217
cycles
4, 6
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks
for the address phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/
IXP46X network processors have had sufficient time to recognize the HRDY and hold the address phase
for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/
IXP46X network processors have had sufficient time to recognize the HRDY and hold the data setup
phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing was designed for a system load between 5pF and 60pF for high drive setting
Data
Valid
Data
Valid
T1
T3
T4
T3
T2
T4
T1 T2
T5
EX_ADDR[2:1]
(hcntl)
EX_RDY_N
(hrdy)
EX_DATA
(hdin)
EX_CS_N
(hcs_n)
EX_W R_N
(hds1_n)
EX_RD_N
(hr_w_n)
EX_CLK
Tadd_setup
Thds1_pulse
Tcs2hds1val
Tdata_setup
Tdata_hold
Trecov
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