參數(shù)資料
型號(hào): EWIXP455ABT
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 266 MHz, RISC PROCESSOR, PBGA544
封裝: LEAD FREE, PLASTIC, BGA-544
文件頁數(shù): 32/163頁
文件大?。?/td> 1123K
代理商: EWIXP455ABT
Electrical Specifications
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
127
5.5.17
All Remaining I/O DC Parameters
5.6
AC Specifications
5.6.1
Clock Signal Timings
5.6.1.1
Processors’ Clock Timings
Table 46.
All Remaining I/O DC Parameters (JTAG, PLL_LOCK)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
Input-high voltage
2.0
V
VIL
Input-low voltage
0.8
V
VOH
Output-high voltage
IOUT = - 4mA
2.4
V
VOL
Output-low voltage
IOUT = 4mA
0.4
V
IIL
Input-leakage current
0 < VIN < VCCP
-10
10
A
CIN
Input-pin capacitance
5
pF
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
2. These parameters are only applicable to signal other than power and ground signals.
Table 47.
Devices’ Clock Timings
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
VIH
Input-high voltage
2.0
V
VIL
Input-low voltage
0.8
V
TFREQUENCY
Clock frequency for IXP45X/IXP46X
network processors oscillator.
33.33
MHz
FREQUENCY
Clock tolerance over -40 C to 85 C.
-50
50
ppm
CIN
Pin capacitance of IXP45X/IXP46X
network processors inputs.
5pF
TDC
Duty cycle
35
50
65
%
NOTES:
1. This value is oscillator input. Use as an oscillator input, tie to the crystal input pin and leave the crystal
output pin disconnected.
2. This parameter applies when driving the clock input with an oscillator.
3. Where the IXP45X/IXP46X network processors are configured with an input reference-clock, the slew rate
should never be faster than 2.5 V/nS to ensure proper PLL operation. To properly guarantee PLL operation
at the slower slew rate, the Vih and Vil levels need to be met at the 33.33MHz frequency.
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