參數(shù)資料
型號： EWIXP455ABT
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 266 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 37/163頁
文件大?。?/td> 1123K
代理商： EWIXP455ABT
Electrical Specifications
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
131
5.6.2.2
USB 1.1 Interface
For timing parameters, see the USB 1.1 specification. The USB 1.1 interface for the IXP45X/
IXP46X network processors supports both a device or function controller only and a host only
controller. The IXP45X/IXP46X network processors USB 1.1 device interface cannot be line-
powered.
To assure proper operation with the IXP45X/IXP46X network processors USB interfaces, please
consult the Intel
IXP45X and Intel IXP46X Product Line of Network Processors Hardware
Design Guidelines and the Intel
IXP4XX Product Line of Network Processors Specification
Update.
Table 53.
PCI Bus Signal Timings
Symbol
Parameter
33 MHz
66 MHz
Units
Notes
Min.
Max.
Min.
Max.
Tclk2outb
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
2111
6
ns
Tclk2out
Clock to output for all point-to-point
signals. This is the PCI_GNT_N
and PCI_REQ_N(0) only.
2121
6
ns
Tsetupb
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
73
ns
Tsetup
Input setup time for all point-to-
point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
10, 12
5
ns
Thold
Input hold time from clock.
0
ns
Trst-off
Reset active-to-output float delay
40
ns
NOTES:
1. See the timing measurement conditions.
2. Parts compliant to the 3.3 V signaling environment.
3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a setup of
12 ns for 33 MHz and 5 ns for 66 MHz.
4. RST# is asserted and de-asserted asynchronously with respect to CLK.
5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. Timing was tested with a 70-pF capacitor to ground.
8. For additional information, see the PCI Local Bus Specification, Revision 2.2.
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