參數(shù)資料
型號: GE28F128W30B90
英文描述: CHIP RESISTOR
中文描述: 的EEPROM | FLASH動畫| 8M × 16位|的CMOS | BGA封裝| 60PIN |塑料
文件頁數(shù): 15/91頁
文件大?。?/td> 994K
代理商: GE28F128W30B90
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
15
3.1
Bus Operations
3.1.1
Read
The 1.8 Volt Intel Wireless Flash memory has several read configurations:
Asynchronous page mode read.
Synchronous burst mode read — outputs four, eight, sixteen, or continuous words, from main
blocks and parameter blocks.
Several read modes are available in each partition:
Read-array mode:
read accesses return flash array data from the addressed locations.
Read identifier mode:
reads return manufacturer and device identifier data, block lock status,
and protection register data. Identifier information can be accessed starting at 4-Mbit partition
base addresses; the flash array is not accessible in read identifier mode.
Read query mode:
reads return device CFI data. CFI information can be accessed starting at
4-Mbit partition base addresses; the flash array is not accessible in read query mode.
Read status register mode:
reads return status register data from the addressed partition. That
partition’s array data is not accessible. A system processor can check the status register to
determine an addressed partition’s state or monitor program and erase progress.
All partitions support the synchronous burst mode that internally sequences addresses with respect
to the input CLK to select and supply data to the outputs.
Identifier codes, query data, and status register read operations execute as single-synchronous or
asynchronous read cycles. WAIT is asserted during these reads.
Access to the modes listed above is independent of V
PP
. An appropriate CUI command places the
device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read-
array mode.
Asserting CE# enables device read operations. The device internally decodes upper address inputs
to determine which partition is accessed. Asserting ADV# opens the internal address latches.
Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous
mode, the address is latched when ADV# is deasserted (when the device is configured to use
Table 4.
Bus Operations
Mode
Notes
RST#
CE#
OE#
WE#
ADV#
WAIT
D[15:0]
Read
4
V
IH
V
IL
V
IL
V
IH
V
IL
See Note
D
OUT
Output Disable
1
V
IH
V
IL
V
IH
V
IH
X
High-Z
High-Z
Standby
1
V
IH
V
IH
X
X
X
High-Z
High-Z
Reset
1,2
V
IL
X
X
X
X
High-Z
High-Z
Write
3
V
IH
V
IL
V
IH
V
IL
V
IL
High-Z
D
IN
NOTES:
1. X must be V
or V
IH
for control pins and addresses.
2. RST# must be at V
± 0.2 V to meet the maximum specified power-down current.
3. Refer to the
Table 6, “Bus Cycle Definitions” on page 19
for valid D
IN
during a write operation.
4. WAIT is only valid during synchronous array read operations.
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