參數(shù)資料
型號(hào): GE28F128W30B90
英文描述: CHIP RESISTOR
中文描述: 的EEPROM | FLASH動(dòng)畫| 8M × 16位|的CMOS | BGA封裝| 60PIN |塑料
文件頁(yè)數(shù): 59/91頁(yè)
文件大?。?/td> 994K
代理商: GE28F128W30B90
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
59
11.0
AC Characteristics
11.1
Read Operations
Table 21. Read Operations (Sheet 1 of 2)
#
Sym
Parameter
1,2
Notes
32-Mbit
64-Mbit
128-Mbit
Unit
-70
-85
-90
Min
Max
Min
Max
Min
Max
Asynchronous Specifications
R1
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
PHQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
OH
Read Cycle Time
7,8
70
85
90
ns
R2
Address to Output Valid
7,8
70
85
90
ns
R3
CE# Low to Output Valid
7,8
70
85
90
ns
R4
OE# Low to Output Valid
4
30
30
30
ns
R5
RST# High to Output Valid
150
150
150
ns
R6
CE# Low to Output Low-Z
5
0
0
0
ns
R7
OE# Low to Output Low-Z
4,5
0
0
0
ns
R8
CE# High to Output High-Z
5
20
20
20
ns
R9
OE# High to Output High-Z
4,5
14
14
14
ns
R10
CE# (OE#) High to Output Low-Z
4,5
0
0
0
ns
Latching Specifications
R101
t
AVVH
t
ELVH
t
VLQV
t
VLVH
t
VHVL
t
VHAX
t
APA
Address Setup to ADV# High
10
10
12
ns
R102
CE# Low to ADV# High
10
10
12
ns
R103
ADV# Low to Output Valid
7,8
70
85
90
ns
R104
ADV# Pulse Width Low
10
10
12
ns
R105
ADV# Pulse Width High
10
10
12
ns
R106
Address Hold from ADV# High
3
9
9
9
ns
R108
Page Address Access Time
25
25
30
ns
Clock Specifications
R200
f
CLK
t
CLK
t
CH/L
t
CHCL
CLK Frequency
40
33
33
MHz
R201
CLK Period
25
30
30
ns
R202
CLK High or Low Time
9.5
9.5
9.5
ns
R203
CLK Fall or Rise Time
3
5
5
ns
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