參數(shù)資料
型號: GE28F128W30B90
英文描述: CHIP RESISTOR
中文描述: 的EEPROM | FLASH動畫| 8M × 16位|的CMOS | BGA封裝| 60PIN |塑料
文件頁數(shù): 36/91頁
文件大小: 994K
代理商: GE28F128W30B90
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
36
Datasheet
The product does not support simultaneous program and erase operations. Attempting to perform
operations such as these results in a command sequence error. Only one partition can be
programming or erasing while another partition is reading. However, one partition may be in erase
suspend mode while a second partition is performing a program operation, and yet another partition
is executing a read command.
Table 5, “Command Codes and Descriptions” on page 17
describes
the command codes available for all functions.
7.0
Security Modes
The 1.8 Volt Intel Wireless Flash memory with 3 Volt I/O offers both hardware and software
security features to protect the flash data. The software security feature is used by executing the
Lock Block command. The hardware security feature is used by executing the Lock-Down Block
command
and
by asserting the WP# signal.
Refer to
Figure 10, “Block Locking State Diagram” on page 37
for a state diagram of the flash
security features. Also see
Figure 11, “Locking Operations Flowchart” on page 39
.
7.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection. The first allows
software-only control of block locking (useful for frequently changed data blocks), while the
second requires hardware interaction before locking can be changed (protects infrequently changed
code blocks).
The following sections discuss the locking system operation. The term “state [XYZ]” specifies
locking states; for example, “state [001],” where X = WP# value, Y = block lock-down status bit
D1, and Z = Block Lock status register bit D0.
Figure 10, “Block Locking State Diagram” on
page 37
defines possible locking states.
The following summarizes the locking functionality.
All blocks power-up in a locked state.
Unlock commands can unlock these blocks, and lock commands can lock them again.
The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP# is
deasserted
— When WP# is asserted, previously locked-down blocks return to lock-down.
— The lock-down status bit is cleared only when the device is reset or powered-down.
Block lock registers are not affected by the V
PP
level. They may be modified and read even if V
PP
V
PPLK
.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the
following sections. See
Figure 11, “Locking Operations Flowchart” on page 39
.
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