- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67672 > GT- 32090 (Galileo Technology Services, LLC) Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁(yè)數(shù)： | 13/67頁(yè) |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)
GT-32090 System Controller For i960JX Processors
20
Galileo
Technology, Inc.
beginning of the cycle to the assertion of the write signals (CSToWr), the number of cycles the write is active (WrAc-
tive), and the number of cycles the write signals are inactive (WrHigh) between consecutive writes in a burst access.
The Ready* signal that can be used to insert wait states to each device data transfer can be enabled/disabled per bank
via the Ready field.
Device Bank0 Parameters, Offset: 0x428
Device Bank1 Parameters, Offset: 0x42c
Device Bank2 Parameters, Offset: 0x430
Device Boot Bank Parameters, Offset: 0x434
Bits
Field name
Function
Initial Value
1:0
TurnOff
The number of cycles between the deassertion of
DevCS* and a new AD bus cycle.
0x3
4:2
AccToFirst
The number of cycles from DevCS* active to first data
(determined by the access time of the device).
Actual value is n+2 (‘00’ is not allowed).
0x7
7:5
AccToNext
The number of cycles between the sampling of data
and the next sampling point of data (time difference
between sampling points in a burst sequence).
Actual value is n+1.
0x7
9:8
CSToWr
The number of cycles from DevCS* to first assertion
of WrEn*
Actual value is n+2 (‘00’ is not allowed).
0x3
11:10
WrActive
The number of cycles WrEn* is active.
Actual value is n+1.
0x3
13:12
WrHigh
The number of cycles between deassertion and
assertion of WrEn*.
Actual value is n+1 (‘00’ is allowed for 32-bit devices
only).
0x3
14
Ready
Controls bus cycle extension, can be disabled by
DevCS*.
0 - Enabled, will extend the bus cycle
1 - Disabled
0x0
15
DevWidth
Determines the width configuration for the device.
0 - The device is configured as 8-bits wide.
1 - The device is configured as 16- or 32- bits wide.
0x1
Bits
Field Name
Function
Initial Value
15:0
Various
Fields function as in Device Bank0.
0xbfff
Bits
Field Name
Function
Initial Value
15:0
Various
Fields function as in Device Bank0.
0xbfff
Bits
Field Name
Function
Initial Value
15:0
Various
Fields function as in Device Bank0.
0xbfff
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-48001A | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| GT-48002A | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器) |
| GT-48004A | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| GT-48006A | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器) |
| GT-48207 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT-32090-A0-PBN-C000 | 制造商:Marvell 功能描述: |
| GT3-20DP-2.5DSA | 制造商:HRS 制造商全稱:HRS 功能描述:Antenna, Sensor, and Communications Trunk Line Connections |
| GT321 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 220pF 3000V SL 5% (20 X 6mm) Radial 9.5mm 85°C |
| GT32-10P-1.5H | 制造商:Hirose 功能描述: |
| GT32-10S-6/CR-MP | 制造商:Hirose 功能描述:902-5118-4-00 EACH 制造商:Hirose 功能描述:GT32-10S-6/CR-MP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。