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| 型號(hào)： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁(yè)數(shù)： | 20/67頁(yè) |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
27
Galileo
Technology, Inc.
3.11
SIO Configuration
These registers configure and control the SIO channels. The registers include: the SIO local Arbiter Control register
that enables several priority options between the DMA channels that are assigned to the SIO; the Channel Flush/Reset
register that enables the CPU to clear the data from the DMA packing and unpacking registers; and the four Channel
Mode registers that define the device parameters (bus width, endianess), the shape of the control signals (pulse width,
burst support, turn-off width), and the DMA parameters (request polarity, arbitration boundaries, DMA direction, DMA
channel assignment). Note that channel 3 does not have DMA capabilities nor burst support. Channel 3 is for
CPU access only.
The Channel Flush/Reset register should only be written to the value of ‘1’. After completion of the Flush/Reset opera-
tion, the appropriate bit will be reset to ‘0’.
Arbiter Control, Offset: 0xc00
Channel Flush/Reset, Offset: 0xc04
Bits
Field name
Function
Initial Value
1:0
PrioChan1/0
Priority between Channel 0 and Channel 1.
00 - Round robin
01 - Priority to channel 1 over channel 0
10 - Priority to channel 0 over channel 1
11 - Reserved
0x0
3:2
Reserved
Must be 0x0
0x0
5:4
PrioGrps
Priority between the group of channels 0&1, and
channel 2.
00 - Round robin
01 - Priority to channel 2 over 0 & 1
10 - Priority to channels 0 & 1 over 2
11 - Reserved
0x0
6
PrioOpt
Defines the arbiter behavior for the high priority device
0 - High priority device will relinquish the bus for a
requesting device for one DMA transaction.
1 - High priority device will be granted as long as it
requests the bus.
0x0
Bits
Field name
Function
Initial Value
0
FlushRstCh0
During an SIO DMA read access, writing ‘1’ will flush
the contents of the packing register into the target
device on the AD bus. During an SIO DMA write
access, writing ‘1’ will clear the unpacking register.
0x0
1
FlushRstCh1
Field functions as in bit 0.
0x0
2
FlushRstCh2
Field functions as in bit 0.
0x0
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