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參數(shù)資料
| 型號： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 59/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
62
Galileo
Technology, Inc.
9 APPLICATIONS: CONNECTING THE MEMORY BUSES
A GT-32090 system can be assembled in different configurations. The DRAM has to be 32-bits wide and the devices
may be 8-, 16-, or 32-bits wide. The user may choose to work with external latches for the DRAM (depending on the
operating frequency) and can choose to work with a bi-directional transceiver for the devices to reduce turn-off time
and the need for drivers on the CPU's AD bus.
9.1 Choosing Standard DRAM or EDO DRAM.
The choice of which type of memory to use is a function of the performance goals for the system. EDO DRAM, being so
common these days, offers an excellent alternative for best performance. Be aware of the following restrictions:
If working with EDO DRAM at 33 MHz you must use a latch for the data.
If working with EDO DRAM at less than 33 MHz you cannot use a latch for the data.
If working with standard DRAM at 33 MHz you cannot use a latch for the data.
If working with standard DRAM at less than 33 MHz you may use a latch for the data (giving you the performance of an
EDO.)
This can be summarized as follows:
9.2 Working Without Data Latches/Transceivers
9.2.1 DRAM Connection
Notes:
1. AD[31:24] is always the MSB and AD[7:0] is always the LSB, regardless of CPU endianess.
Memory
Type
Frequency
Latch
Performance
EDO
33MHz
25MHz
20MHz
16MHz
Required
Not Allowed
xxDDDD
xDDDD
DDDD
DRAM
33MHz
25MHz
20MHz
16MHz
Not Allowed
Optional
xxDxDxDxDx
xDDDD (latches), xxDxDxDxDx (no latches)
DDDD (latches), xxDxDxDxDx (no latches)
Connection
Memory
Width
Connect...
To...
DRAM Address
32-bit
DAdr[10:0]
DRAM address pins
DRAM Data1
32-bit
AD[31:0]
DRAM data pins
DRAM Control
32-bit
RAS[3:0]*
CAS[3:0]*
DWr*
DRAM RAS pins
DRAM CAS pins
DRAM write pins
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