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| 型號(hào)： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁(yè)數(shù)： | 17/67頁(yè) |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
24
Galileo
Technology, Inc.
Channel 0 Control, Offset: 0x840
Bits
Field name
Function
Initial Value
0
FlyBy
Selection of fly-by or normal operation.
0 - No fly-by mode, data is read into the DMA’s FIFO
and then written to the destination address.
1 - Fly-by mode, data is transferred to/from devices on
the AD Bus to/from DRAM
0x0
1
FlyByDir
This bit is meaningful only in fly-by mode.
0 - Read from DRAM
1 - Write to DRAM
0x0
3:2
SrcDir
Source Direction.
00 - Increment source address
01 - Decrement source address
10 - Hold in the same value
11 - Not allowed
0x0
5:4
DestDir
Destination Direction.
00 - Increment destination address
01 - Decrement destination address
10 - Hold in the same value.
11 - Not allowed
0x0
8:6
DataTransLim
Data Transfer Limit in each DMA access.
000 - 4 bytes
001 - 8 bytes
011 - 16 bytes
111 - Reserved
0x0
9
ChainMod
Chained Mode.
0 - Chained mode; when a DMA access is terminated,
the parameters of the next DMA access will come
from a record in memory that a NextRecPtr register
points to.
1 - Non-chained mode; only the values that are pro-
grammed by the CPU directly into the ByteCt, SrcAdd,
and DestAdd registers are used.
0x0
10
IntMode
Interrupt Mode.
0 - Interrupt asserted every time the DMA byte count
reaches terminal count.
1 - Interrupt every NULL pointer (in Chained mode).
0x0
11
TransMod
Transfer Mode.
0 - Demand
1 - Block
0x0
12
ChanEn
Channel Enable.
0 - Disable the channel for DMA accesses
1 - Enable the channel for DMA accesses
0x0
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