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參數(shù)資料
| 型號(hào)： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 7/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
15
Galileo
Technology, Inc.
3.2 Group Address Space
There are eight main address space segments that the GT-32090 decodes. The segments are DRAM, four AD
devices, PCMCIA, SIO devices, and Internal registers.
DRAM Address Space, Offset: 0x000
Device 0 Address Space, Offset: 0x004
Device 1 Address Space, Offset: 0x008
Device 2 Address Space, Offset: 0x00c
Boot Device Address Space, Offset: 0x010
Bits
Field Name
Function
Initial Value
4:0
Decode
The DRAM banks will be accessed when AD bits
31:27 match the value programmed in bits 4:0.
0x00
Bits
Field Name
Function
Initial Value
6:0
Decode
The AD device bank will be accessed when AD bits
31:25 match the value programmed in bits 6:0.
{DMAReq[2:0],1,1,1,1}
* Bits [6:4] are sampled
during reset from pins
DMAReq[2:0].
Bits
Field Name
Function
Initial Value
6:0
Decode
The AD device bank will be accessed when AD bits
31:25 match the value programmed in bits 6:0.
{DMAReq[2:0],1,1,1,1}
* Bits [6:4] are sampled
during reset from pins
DMAReq[2:0].
Bits
Field Name
Function
Initial Value
6:0
Decode
The AD device bank will be accessed when AD bits
31:25 match the value programmed in bits 6:0.
{DMAReq[2:0],1,1,1,1}
* Bits [6:4] are sampled
during reset from pins
DMAReq[2:0].
Bits
Field Name
Function
Initial Value
6:0
Decode
The AD device bank will be accessed when AD bits
31:25 match the value programmed in bits 6:0.
{DMAReq[2:0],1,1,1,1}
* Bits [6:4] are sampled
during reset from pins
DMAReq[2:0].
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