參數(shù)資料
型號(hào)： GT- 32090
廠商： Galileo Technology Services, LLC
英文描述： Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器)
中文描述： 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器）
文件頁(yè)數(shù)： 45/67頁(yè)
文件大?。?/td> 524K
代理商： GT- 32090
GT-32090 System Controller For i960JX Processors
5
Galileo
Technology, Inc.
Ready*
I
Ready: When not active, it extends the access to a device on the
AD bus by adding wait cycles.
BufOE*
O
Buffer Output Enable: This signal has similar functionality to the
DEN* signal of the i960JX, but is active during accesses to devices
only. It is active during the data phase of accesses to devices on the
AD bus. It is used with the W/R* to control external data transceiv-
ers.
PCMCIA & SIO
Shared Signals
P/SAddr[1:0]
O
PCMCIA/SIO Address: Byte and half-word addresses for PCMCIA
and SIO accesses.
P/SData[15:0]
I/O
Data Bus: Shared data bus for SIO and PCMCIA devices.
SIO Interface
SBE[1:0]*
O
SIO Byte Enable: Selects which of the two bytes on the SIO bus
participates in the current data transfer.
SCS[3:0]*
O
SIO Chip Select: Chip Select for devices on the SIO bus.
SRd*
O
SIO Read: Active during a read from a device on the SIO bus.
SWr*
O
SIO Write: Active during a write to a device on the SIO bus.
SWait*
I
SIO Wait: Extends bus cycle, used to generate wait states by SIO
devices.
PCMCIA Card A
CardEnA[2:1]*
O
Card Enable A: CardEnA[1] enables the even address bytes, and
CardEnA[2] enables the odd address bytes.
OEA*
O
Output Enable A: Controls the output of data from card.
WaitA*
I
Wait A: Extends bus cycle, used to generate wait states by the
card.
WrEnA*
O
Write Enable A: Indicates write accesses by the GT-32090 to the
card.
IORdA*
O
I/O Read A: Activated to read data from the card’s I/O space.
IOWrA*
O
I/O Write A: Activated to write data to the card’s I/O space.
PCMCIA Card B
CardEnB[2:1]*
O
Card Enable B: CardEnB[1] enables the even address bytes, and
CardEnB[2] enables the odd address bytes.
OEB*
O
Output Enable B: Controls the output of data from card.
WaitB*
I
Wait B: Extends bus cycle, used to generate wait states by the
card.
WrEnB*
O
Write Enable B: Indicates write accesses by the GT-32090 to the
card.
IORdB*
O
I/O Read B: Activated to read data from the card’s I/O space.
IOWrB*
O
I/O Write B: Activated to write data to the card’s I/O space.
DMA
ADBusReq
I
Bus Request: Signals a request from the external agent to the GT-
32090 for acquisition of the AD bus.
Pin Name
Type
Description
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