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參數(shù)資料
| 型號： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 60/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
63
Galileo
Technology, Inc.
9.2.2 Device Connection
Notes:
1. LAdd[25:2] is the output of the 373 address latches sampled by the ALE signal of the CPU’S AD bus.
2. A2 is the A2 bit of the CPU.
3. AD[31:24] is always the MSB and AD[7:0] is always the LSB, regardless of endianess.
4. AD[15:8] is always the MSB and AD[7:0] is always the LSB, regardless of endianess.
5. WrEn[3]* is for AD[15:8], WrEn[0]* is for AD[7:0].
9.3 Working With Data Latches/Transceivers
9.3.1 DRAM Connection
Notes:
1. AD[31:24] is always the MSB and AD[7:0] is always the LSB, regardless of CPU endianess.
2. Must have a 32 bi-directional latch (such as 2 IDTFCT16543).
Connection
Memory
Width
Connect...
To...
Device Address
32-bit
16-bit
8-bit
{ LAdd[24:4]1, DAdr[1:0] }
{ LAdd[24:3]1 , A22 , BE[1]* }
{ LAdd[24:2]1 , BE[1:0]* }
Device address pins
Device Data
32-bit
16-bit
8-bit
AD[31:0]3
AD[15:0]4
AD[7:0]
Device data pins
Device Control
32-bit
16-bit
8-bit
WrEn[3:0]*
WrEn[3]*, WrEn[0]*5
WrEn[0]*
Device write pins
Connection
Memory
Width
Connect...
To...
DRAM Address
32-bit
DAdr[10:0]
DRAM address pins
DRAM Data1,2
32-bit
AD[31:0]
Latch I/O’s A side
Latch I/O’s B side
DRAM data pins
DRAM Control
32-bit
RAS[3:0]*
CAS[3:0]*
DWr*
‘0’
LWrOE*
LRdOE*
Clock
LE*
DRAM RAS pins
DRAM CAS pins
DRAM Write pins
CEAB* of 543 data latches
CEBA* of 543 data latches
OEBA* of 543 data latches
OEAB* of 543 data latches
LEBA* of 543 data latches
LEAB* of 543 data latches
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