參數(shù)資料
型號： GT- 32090
廠商： Galileo Technology Services, LLC
英文描述： Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器)
中文描述： 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器）
文件頁數(shù)： 19/67頁
文件大小： 524K
代理商： GT- 32090
GT-32090 System Controller For i960JX Processors
26
Galileo
Technology, Inc.
3.10 DMA Arbiter
The DMA controller has a programmable arbitration scheme between its three channels. The channels are grouped
into two groups, one group includes channel 0 and 1, and the other group includes only channel 2. The channels in the
first group can be programmed so that one of them will have the higher priority, or they can both have the same priority
in round robin fashion. The priority between the two groups can be programmed in a similar way so that a selected
group has a higher priority, or they can both have the same priority in round robin.
The priority scheme has additional flexibility with the programmable Priority Option. With the Priority Option the DMA
bandwidth allocation can be divided in a fairer way. For example, if the PrioOpt bit is set to ‘0’ and the PrioGrps field is
set as ‘10’, the requesting devices will get the DMA in the order 0,1,2,0,1,2,0,1,2,0,1,2,..... (assuming that PrioChan1/0
is set to round robin), while if the PrioOpt bit is set to ‘1’ the requesting devices will get the DMA in the order
0,1,0,1,0,1,2,2,2,..... The DMA arbiter control register can be reprogrammed any time regardless of the channels’ sta-
tus (active or not active).
Some arbitration examples follow to facilitate the understanding of this register:
1. Assuming all 3 channels are requested all the time,
with Arbiter Control register = 0x40, the order will be: 0,2,1,2,0,2,1,2,0,2,1,2,.....
with Arbiter Control register = 0x0, the order will be: 0,1,2,0,1,2,0,1,2,.....
2. Assuming all 3 channels are requested all the time ,
with Arbiter Control register = 0x51, the order will be: 2,2,2,2,..1,1,1,1,...,0,0,0,0,.....
with Arbiter Control register = 0x11, the order will be: 2,1,2,0,2,1,2,0,.....
3. Assuming all 3 channels are requested all the time,
with Arbiter Control register = 0x50, the order will be: 2,2,2,2,....,1,0,1,0,...
with Arbiter Control register = 0x10, the order will be: 2,0,2,1,2,0,2,1,.....
Arbiter Control, Offset: 0x860
Bits
Field name
Function
Initial Value
1:0
PrioChan1/0
Priority between Channel 0 and Channel 1.
00 - Round robin
01 - Priority to channel 1 over channel 0
10 - Priority to channel 0 over channel 1
11 - Reserved
0x0
3:2
Reserved
Must be 0x0
0x0
5:4
PrioGrps
Priority between the group of channels 0&1, and
channel 2.
00 - Round robin
01 - Priority to channel 2 over 0&1
10 - Priority to channels 0&1 over 2
11 - Reserved
0x0
6
PrioOpt
Defines the arbiter behavior for the high priority
device.
0 - High priority device will relinquish the bus for a
requesting device for one DMA transaction.
1 - High priority device will be granted as long as it
requests the bus.
0x0
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