參數(shù)資料
型號(hào)： GT- 32090
廠商： Galileo Technology Services, LLC
英文描述： Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器)
中文描述： 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器）
文件頁數(shù)： 34/67頁
文件大?。?/td> 524K
代理商： GT- 32090
GT-32090 System Controller For i960JX Processors
4
Galileo
Technology, Inc.
1.2
Pin Assignment Table
Pin Name
Type
Description
CPU Interface
AD[31:0]
I/O
Address/Data Bus: Multiplexed address and data bus for commu-
nication between the processor, devices, DRAM, any external
agent, and the GT-32090.
ALE
I/O
Address Latch Enable: A strobe for latching the address into the
GT-32090 and into external latches for devices, PCMCIA cards, and
SIO bus peripherals. It is an input during a CPU or external agent
access, and an output during a DMA access.
ADS*
I/O
Address Strobe: Indicates a valid address and the start of a new
bus access. It is an input during a CPU or external agent access,
and an output during a DMA access.
BE[3:0]*
I/O
Byte Enable: Selects which of the four bytes on the AD bus partici-
pate in the current bus access. It is an input during a CPU or exter-
nal agent access, and an output during a DMA access.
Hold
O
Hold: A request from the GT-32090 to acquire the AD bus.
HoldA
I
Hold Acknowledge: An indication by the CPU that it has relin-
quished the AD bus to the GT-32090.
RdyRcv*
O
Ready/Recover: Indicates when the data on the AD bus can be
sampled or removed. During a device turn-off time, it indicates to
the CPU not to drive the address on the AD bus.
W/R*
I/O
Write/Read: Specifies if the access is a write or a read access. It is
an input during a CPU or external agent access, and an output dur-
ing a DMA access. Used also to control the direction of the bi-direc-
tional transceiver for the devices on the AD bus.
DRAM
DAdr[10:0]
O
DRAM Address/Device Burst Address: Eleven multiplexed
address bits to the DRAM. DAdr[1:0] provides the word burst
address (same meaning as the CPU’s A3, A2 pins) for all 32-bit
accesses, be they to DRAM or to devices.
RAS[3:0]*
O
Row Address Select: Supports four banks of DRAM.
CAS[3:0]*
O
Column Address Select: Supports byte writes to DRAM.
DWr*
O
DRAM Write: Signals a write access to the DRAM.
LE*
O
Latch Enable: When active, latches the DRAM data into external
latches.
LRdOE*
O
Latch Read Output Enable: When active, outputs the data from
the DRAM’s external latches onto the AD bus.
LWrOE*
O
Latch Write Output Enable: When active, outputs the data from
the DRAM’s external latches onto the DRAM’s data pins.
AD Bus Devices
WrEn[3:0]*
O
Write Enable: Byte write enable to devices on the AD bus.
DevCS[2:0]*
O
Device Chip Select: Programmable chip select signals to devices
on the AD bus.
BootCS*
O
Boot Chip Select: Programmable chip select signal to the boot
device on the AD bus.
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