參數(shù)資料
型號: GT- 32090
廠商: Galileo Technology Services, LLC
英文描述: Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器)
中文描述: 高度集成的單芯片系統(tǒng)控制器(高集成單片系統(tǒng)控制器)
文件頁數(shù): 21/67頁
文件大?。?/td> 524K
代理商: GT- 32090
GT-32090 System Controller For i960JX Processors
28
Galileo
Technology, Inc.
Channel 0 Mode, Offset: 0xc08
Bits
Field name
Function
Initial Value
0
DMASel
Selects if the DMA is to an SIO device or to an AD bus
device.
0 - AD bus DMA
1 - SIO bus DMA
0x0
1
BusWid
The data path width of the device on the SIO.
0 - 8-bits
1 - 16-bits
0x0
2
Endian
Defines the device byte ordering.
0 - Little endian
1 - Big endian
0x0
3
ArbBound
This bit defines whether the channel arbitrates for the
SIO bus during a DMA operation every access (byte
or 16-bit word) or only when the DMA is finished pack-
ing or unpacking its register.
0 - Every access
1 - Every word
0x0
4
BurstMode
Selects if the DMAAck* corresponding to this channel
will stay LOW through a burst DMA or will be deas-
serted after every read or write. In Burst Mode, the
strobe signal (i.e. SWr*, SRd*) is deasserted for one
cycle during the access.
0 - DMAAck* does not stay LOW
1 - DMAAck* stays LOW
0x0
5
WrRd
Defines the DMA direction.
0 - Read from an SIO device
1 - Write to an SIO device
0x1
9:6
PulsWid
Pulse width, the number of cycles the SRd* or SWr*
signals will be asserted. The actual number will be
n+1.
0xf
11:10
TOWid
Turn-Off width, the number of cycles between the
deassertion of the SCS* corresponding to this chan-
nel in a read access and
a) the start of a read cycle to a PCMCIA card or to an
SIO device, or
b) a write access to a PCMCIA card or an SIO device.
0x3
12
DMAReqPol
Selects the polarity of the DMAReq signal corre-
sponding to this channel.
0 - Active HIGH
1 - Active LOW
0x0
13
TotalMask
When this bit is ‘1’ the corresponding DMAReq is
masked.
0 - Enable DMA request.
1 - Mask DMA request.
0x1
14:17
ByteEn
Byte enables of the packing/unpacking register.
These bits are read only. This field is only relevant for
unpacking.
oxf
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