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參數(shù)資料
| 型號： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 67/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
9
Galileo
Technology, Inc.
DRAM with assertion of DevCS*, DMAAck*, and WrEn*,
if necessary. The WrEn* signals are not toggled. The
length of each DMA access can be limited to 1, 2, or 4
32-bit words.
For a 32-bit device, the write signals are WrEn[3:0]*. For
a 16-bit device, the write signals are WrEn[3]* for write
high byte, and WrEn[0]* for write low byte. For an 8-bit
device, the write signal is WrEn[0]*.
The SIO bus DMA can transfer data between an 8- or 16-
bit wide device on the SIO bus, and a 32-bit wide device/
DRAM on the AD bus. In read accesses (from an SIO
device to an AD bus device), the SIO DMA uses one of
three internal packing registers (one for each channel),
that pack 8- or 16-bit data into 32-bit words. In write
accesses (from an AD bus device to an SIO device), the
SIO DMA uses one of three internal unpacking registers
(one for each channel), that unpack 32-bit words into 8-
or 16-bit data.
The SIO channel can be programmed as read (source) or
write (destination) depending on bit 5 of the Channel
Mode register.
During an SIO DMA, data is transferred in two stages
that involve one of the SIO local packing and unpacking
registers, and the FIFO in the AD DMA unit.
During an SIO DMA read access, the SIO device will
arbitrate for the SIO bus in the local SIO arbiter, and will
move data into its channel packing register. When the
register is full, or when the DMA counter reaches terminal
count, the packing register will arbitrate in the AD DMA
arbiter for the AD DMA FIFO, and will transfer the data to
it. When the data is in the FIFO, the FIFO will request the
AD bus and will transfer data to the AD bus device.
During an SIO DMA write access, the AD DMA will move
data from the AD bus to its internal FIFO. From the FIFO,
it will move the data into the SIO unpacking register, and
then the SIO DMA will unpack and transfer the data to
the requesting SIO device.
The SIO packing/unpacking register can be flushed by
writing to the Channel Flush/Reset register (see section
3.11).
The SIO channel can be programmed to two possibilities
of arbitration:
1) Access Arbitration: Arbitration between SIO chan-
nels is done in every SIO DMA access (byte or 16-bit
word).
2) Word Arbitration: Arbitration between SIO channels
is done only when the DMA finishes packing/unpacking
its register (four byte transfers or two 16-bit word trans-
fers).
The DMA controller supports chained and non-chained
modes of operation. In the non-chained mode, the CPU
programs the DMA channel for each DMA transaction. In
chained mode, the DMA controller programs itself for the
next DMA operation by fetching the information from a
linked list of records in memory.
The DMA controller can be programmed to assert an
interrupt in chained mode, at the end of every DMA trans-
action or when the Next Pointer Register is NULL and
Byte Count reaches terminal count. In non-chained
mode, the DMA will assert an interrupt every time the
Byte Count reaches terminal count.
There are two separate arbiters for DMA accesses. One
arbiter prioritizes accesses between devices on the SIO
bus for data transfers between SIO devices and their
packing/unpacking registers. The second arbiter priori-
tizes accesses between devices on the AD bus and SIO
devices. The two arbiters have programmable priorities
and are identical in their functionality. The arbiter pro-
grammable options work as follows: Channels 0 and 1
are in one group, and channel 2 in the second group.
Inside the two channel group, the priority can be fixed
with a selected channel number having the higher prior-
ity, or both can have the same priority in round robin fash-
ion. The same scheme applies between the two groups,
they can have fixed or round robin priority.
In systems with EDO DRAM at 33MHz or Page Mode
DRAM at 16 to 25MHz that require high bandwidth, the
data phase should be extended. In order to extend the
data phase, a bi-directional latch should be used. The
GT-32090 controls the latch- read output enable (DRAM
Data to CPU Bus), write output enable (CPU Data to
DRAM Data), read latch enable (DRAM Data). The latch-
ing at the CPU bus is done with the use of the system
clock. The correct timing of the controls is derived from
the system’s parameters - ADFreq, Type, and Latch,
which are programmed in the DRAM Parameters regis-
ter.
2.6
SIO
The SIO interface is a simple Read/Write with Chip
Select bus interface. The interface includes: a dedicated
16-bit wide data bus that is shared with the PCMCIA
devices, an address bus that is shared with the AD bus
devices, dedicated byte and 16-bit word address, byte
enables (SBE[1:0]*), four chip selects (SCS[3:0]*), read
(SRd*) and write (SWr*) control signals, and a flow con-
trol signal (SWait*), in addition to the DMA signals.
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