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參數(shù)資料
| 型號： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 16/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
23
Galileo
Technology, Inc.
Channel 0 Next Record Pointer, Offset: 0x830
Channel 1 Next Record Pointer, Offset: 0x834
Channel 2 Next Record Pointer, Offset: 0x838
3.9
DMA Channel Control
Each DMA channel has a control register to set its mode of operation independently of the other two channels. A chan-
nel can be programmed to transfer data through the GT-32090 (internal) or directly between DRAM and devices (fly-
by). In the internal mode, the DMA reads data from the source address (SIO, devices or DRAM) into an internal 16-byte
FIFO. From the internal FIFO, the data is written to a destination address (SIO, devices or DRAM) that can be indepen-
dent from the source address. In fly-by mode, data can be transferred only between a 32-bit wide DRAM and a 32-bit
device through the AD bus. The DMA controller will generate addresses for the DRAM and DMAAck* for the device.
Transfer direction (DRAM to device or device to DRAM) has to be programmed in the Control register’s FlyByDir field.
Source addresses and destination addresses can be programmed to increment, decrement, or hold the same value
throughout the DMA transfer. For devices that can absorb a limited number of bytes at a time, the channel can be pro-
grammed to limit the number of bytes transferred in each DMA cycle. DMA accesses can be initiated by an external
source (Demand mode) by asserting one of the three DMAReq[2:0] pins, or by an internal request (Block mode) until
the byte count reaches zero.
All three channels have chaining support via linked lists of records. When the chaining mode is enabled, the DMA con-
troller will fetch the information (the record) for a new DMA transfer directly out of memory without involving the CPU.
The location of the next record is in the Next Record Pointer register (NextRecPtr) and the DMA controller will fetch
records every DMA transfer end until it reaches the NULL pointer (NULL pointer is zero).
There are several mechanisms for status and control of the DMA operations. A status interrupt can be programmed to
be asserted every time the DMA byte count reaches zero, or only when byte count reaches zero and the record is the
last record in the chain (the NextRecPtr is NULL). In addition, there is a status bit that indicates whether a channel is
active or not. A channel is active when it is enabled and its byte count is other than zero, or in chained mode when both
its byte count is not equal to zero or its NextRecPtr is not equal to NULL, or when it is disabled and its internal FIFO is
not empty. A channel can be controlled by disabling it temporarily, and a next record fetch can be forced in chained
mode even if the current DMA has not ended.
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
Bits
Field Name
Function
Initial Value
31:0
NextRecPtr
The address for the next record of DMA. A value of 0
means a NULL pointer (end of the chained list).
0x0
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