參數(shù)資料
型號(hào)： GT- 32090
廠商： Galileo Technology Services, LLC
英文描述： Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器)
中文描述： 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器）
文件頁(yè)數(shù)： 66/67頁(yè)
文件大?。?/td> 524K
代理商： GT- 32090
GT-32090 System Controller For i960JX Processors
8
Galileo
Technology, Inc.
For systems that require more than 64MBytes of DRAM,
it is possible to add 4 more DRAM banks with a simple
external multiplexer, to get to a total of 128MBytes of
DRAM with 8 RAS control signals, using Address[26] to
multiplex between two banks. For instance, the demulti-
plexing can be implemented with a Quality Semiconduc-
tor QS3257.
2.4
AD Bus Device Controller
The GT-32090 supports directly four devices on the AD
bus, one boot device and three general purpose devices
such as Flash, SRAM, ROM, FIFO, or any other read/
write peripheral device. External logic can sub-decode
the four chip selects to any number, using the Address for
the sub-decoding. The device controller has several con-
trol signals to enable read and write accesses (including
chip selects, reads, writes, and buffer control). Each Chip
Select has a programmable address space of 2MBytes to
32MBytes to enable contiguous address space between
the different banks. Byte writes are enabled through four
Write Enable signals. The write signals can be shaped by
specifying in the Device Bank Parameters registers the
following: the number of cycles from the assertion of
DevCS* to the first assertion of write (CsToWr); the num-
ber of cycles the write pulse is active (WrActive); and the
number of cycles the write signal is non-active between
consecutive writes(WrHigh). The timing parameters of
the write signals determine the length of active DevCS*
and DMAAck* (when allocated to an AD bus device).
In read cycles, the following parameters are programma-
ble: the number of cycles from the assertion of Chip
Select to the rising edge of the clock that samples the
first data (DelayToFirst), the number of cycles from when
data is sampled to the next time data is sampled (Delay-
ToNext); and the number of cycles between the deasser-
tion of DevCS* to a new AD bus cycle (TurnOff).
Each device can be configured as 8-, 16- or 32-bits wide,
by programming the appropriate i960Jx’s PMCON regis-
ter to the desired bus width, and mapping the appropriate
Device n Address Space decode register into this
address space. Each PMCON configures the bus width
of a memory region with a specific Addr[31:29] while the
Device n Address Space decode register maps device #n
into a region with a specific Addr[31:25].
The device controller supports read or write bursts of up
to four data elements. The burst address is supported by
a 2-bit wide address bus that is multiplexed with the two
least significant bits of the DRAM address (DAdr[1:0])
when the device is 32-bits wide. For an 8-bit device the
burst address is the CPU’s BE[1:0]*, and for a 16-bit
device the burst address is the CPU’s {A2, BE[1]*}. For
an 8-bit device the write signal is WrEn[0]*, and for a 16-
bit device the write signals are WrEn[3]* (Write High
Byte) and WrEn[0]* (Write Low Byte).
The Ready* pin enables an extension of a device cycle
beyond the values that are programmed in the Device
Bank Parameters register. All the control signals will con-
tinue to be in their state when the Ready* signal is sam-
pled inactive, and until it becomes active. The internal
state machine counters will continue to count to the pro-
grammed values, even when Ready* is HIGH. The con-
trol signals will change only when the Ready* is LOW and
the counters are at terminal count. After insertion of wait
states and re-assertion of Ready*, there are two clock
cycles to data transfer. The use of the Ready* signal is
individually optional for each bank through a programma-
ble bit in the Device Bank Parameters registers.
In systems where the devices on the AD bus represent a
large load, or where there are devices with long turn-off
times, the GT-32090 supports an optional bi-directional
transceiver (245 type) to isolate the device bus from the
CPU’s AD bus. The BufOE* signal controls the bi-direc-
tional transceiver’s OE* and the W/R* signal controls its
direction.
2.5
DMA
The DMA controller can move data between devices on
the AD bus, or between devices on the AD bus and
devices on the SIO bus. There are two DMA subsystems
on the GT-32090, one handles the DMA activity on the
SIO bus, and the other handles the activity on the AD
bus. Each DMA subsystem has its own data storage
resources and arbiters. The two DMA subsystems can
work simultaneously or independently, except for the time
that they transfer data between the SIO bus and the AD
bus. Both subsystems can have at one time three DMA
channels active. Each of the three channels can be allo-
cated to service the SIO bus or the AD bus.
DMA accesses can be initiated by an external request by
asserting one of the three DMAReq pins (Demand
mode), or by setting an internal bit in a register (Block
mode). Access can be non-aligned both at the source
and at the destination, and up to 64KBytes of data can be
transferred in each transaction.
The AD bus DMA can transfer data in two ways: through
an internal 16-byte FIFO, or directly between the DRAM
and an AD bus device (“fly-by”). In the internal mode,
data is transferred from the source device/DRAM into the
internal FIFO, and from the internal FIFO to the destina-
tion device/DRAM. In “fly-by” mode, the access is to
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