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參數(shù)資料
| 型號： | GT- 32090 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| 中文描述： | 高度集成的單芯片系統(tǒng)控制器（高集成單片系統(tǒng)控制器） |
| 文件頁數(shù)： | 25/67頁 |
| 文件大?。?/td> | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
31
Galileo
Technology, Inc.
4 RESTRICTIONS
4.1 CPU Interface
a) The DRAM space must be configured as a 32-bit bus
in the i960Jx’s registers.
b) The SIO and the PCMCIA bus must be configured as a
16-bit bus in the i960Jx’s registers. Configuring 8-bit
devices is possible by programming the GT-32090’s reg-
isters only.
c) The GT-32090’s internal registers space must be con-
figured as a 32-bit bus in the i960Jx’s appropriate
PMCON register.
4.2 AD Bus Device Controller
a) When signal shaping parameters like WrActive,
AccToFirst, AccToNext are programmed to their minimum
allowed values, the Ready* signal will be ignored during
the relevant time.
b) The minimum allowed values of the parameters
CSToWr and AccToFirst is 1 (i.e 3 clock cycles).
c) The minimum allowed value of the parameter WrHigh
is 1 when the device is either 8- or 16-bits wide, and 0
when it is 32-bits wide.
4.3 DMA
a) DMA transactions which involve the SIO require the
address bits [1:0] of both source and destination to have
the same value.
b) For DMA on the SIO bus, when the SIO channel is
configured to Burst Mode, source and destination
addresses, as well as byte count, must be word-aligned.
c) There is DMA support only for an AD bus device which
is 32-bits wide.
d) For each transfer, the minimum byte count is 4. For
DMA to/from the SIO, the field DataTransLim in the DMA
Channel Control register is restricted to the value ‘000’ -
a maximum of 4 bytes.
e) In order to restart a channel after it has been enabled,
it should first be checked that the DMAActSt bit is set to
NOT ACTIVE (see section 3.9 for details).
f) When the source or destination address is decre-
mented, both addresses should be word-aligned (that is,
A1 and A0 should be both zero), and Byte Count should
be a multiple of 4.
g) When using the address Hold option in the source
direction (SrcDir in section 3.9), the source address
should be word-aligned.
h) When using the address Hold option in the destination
direction (DestDir in section 3.9), both Source and Desti-
nation addresses should be word-aligned.
i) Records’ addresses (NextRecPtr) should be a multiple
of 16.
j) In fly-by mode, both source and destination addresses
should be word-aligned (that is, A1 and A0 should be
both zero), and byte count should be a multiple of 4.
k) When the DMA is programmed to Demand mode (with
or without SIO channel), first the DMA registers should
be programmed and then the corresponding SIO register
(Channel Mode register).
l) For DMA on the SIO bus, the SIO register (Channel
Mode register) should be programmed last in a Configu-
ration of DMA process. In a Re-configuration of DMA with
an SIO device this register should be written twice: once
with a ‘0’ value to bit 0 (DMASel) and then with a ‘1’ value
to that same bit, precisely in this sequence.
4.4 SIO & PCMCIA
a) When the parameter PulsWid is programmed to less
then 2 (i.e. less then 3 clock cycles) the appropriate Wait*
signal will be ignored during the assertion of the read or
write signals.
4.5 Memory Mapping
a) When the same value is programmed to two or more
of the Device n Address Space registers (which configure
bits[31:25] of device #n’s address space), the regions
corresponding to their CS[n] Decode Address registers
(which configure High and Low values to bits[24:21] of
device #n’s address space) must not be overlapped.
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