參數(shù)資料
型號(hào)： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 15/162頁
文件大小： 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
111 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Ingress WATERMARK Register
There are 2 registers for SPI-4 main interface.
SPI-4 Ingress Training to out of sync threshold Register
SPI-4 Egress LID To LP Mapping Table
There are 128 table entries for SPI-4 main interface and 64 table entries for SPI-4 tributary interface.
SPI-4 Egress Calendar 0 Table
There are 128 table entries for SPI-4 main egress and 64 table entries for SPI-4 tributary egress calendar_0 to schedule the updating of the status
channel LPs to the attached device
Field
Read /
Write
Bits
Length Reset
State
Description
WATERMARK
R/W
0:0-0:4
5
0x0d
Sets the watermark value per PFP.This indicates that if “WATERMARK” number of
ingress lockers are full, then backpressure will be initiated for all LIDs on a SPI-4
ingress interface.
Note:(1) 0x1F is the highest watermark that can be set, meaning that the ingress buffer will be full before backpressure will be initiated on a SPI-4 ingress inter
face PFP. A WATERMARK field value of 0x0F is used to set a watermark for a half-full ingress buffer before tripping backpressure.
(2) Per LID backpressure is set in fields THR_STARV and THR_HUNG in the PFP Buffer Segment Assign Table (p. 120)
Table 70
SPI-4 Ingress Watermark Register (Block Base=0x0300, Register Offset=0x0F-0x10)
Field
Read /
Write
Bits
Length
Reset
State
Description
STRT_TRAIN
R/W
0:0-0:7
8
0
!=0: If this field is not equal to zero, then the ingress interface
goes out of sync if more than STRT_TRAIN times consecutive
training pattern is received on its data channel.
Table 71
Ingress Training to out of sync threshold Registe(Block Base=0x0300,Register Offset=0x13)
Field
Read /
Write
Bits
Length Reset
State
Description
LP
R/W
0:0-0:7
8
0
LP number. LID to LP map is used to map a LID used internally to a SPI-4 egress
logical port.
EN
R/W
1:0
1
0
The EN bit is used to enable or disable the connection of a LID to an LP.
0=LP is disabled
1=LP is enabled
Note: The LID number is equal to the register offset.
Table 72
SPI-4 Egress LID To LP Mapping Table (Block Base=0x0400, Register Offset=0x00-0x3F/0x7F)
Field
Read /
Write
Bits
Length Reset
State
Description
LP
R/W
0:0-0:7
8
0xFF
The Logical Port value programmed in this field, schedules a status channel update
according to the calendar sequence.
Table 73
SPI-4 Egress Calendar 0 Table (Block Base=0x0500, Register Offset=0x00-0x3F/0x7F)
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