參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 37/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
131 of 162
October 20, 2006
IDT IDT88K8483
External Memory Test Results Register
Auxiliary Early Backpressure Threshold Register
Auxiliary Packet Mode Configuration Register
HSTL Test Register
Field
Read /
Write
Bits
Length Reset
State
Description
TEST_DONE
R
0:0
1
This field indicates the status of the external QDR-II SRAM built-in self test.
0: Test in progress. This bit is set to 0 when the test is triggered by writing 1 to the
field TEST in Table 121.
1: Test finished.
ERROR
R
0:1
1
0
This field indicates the result of the external QDR-II SRAM test.
0: No error.
1: Some error with memory BIST.
Table 122 External Memory Test Results Register
(Block Base=0x0A00, Register Offset=0x05)
Field
Read /
Write
Bits
Length Reset
State
Description
EBP_THR
R/W
0:0-1:5
14
0x40
In the PFP to QDR-II path, this field programs the threshold in the QDR-II FIFO at
which backpressure will be generated. If free space in the FIFO is less than this
threshold, backpressure is initiated towards the PFP egress by setting the FIFO sta-
tus to satisfied. This threshold is a global setting that is used by all FIFOs in the
QDR-II SRAM.
Table 123 Auxiliary Early Backpressure Threshold Register
(Block Base=0x0A00, Register Offset=0x07)
Field
Read /
Write
Bits
Length Reset
State
Description
PKT_MODE
R/W
0:0
1
0
This bit controls the mode of transfer from QDR-II to PFP ingress.
0: Cut through mode. In this mode, contiguous transfers from the QDR-II SRAM to
the PFP may contain interleaved packets.
1: Packet mode.In this mode, whole packets are transferred from the QDR-II SRAM
to PFP.
Table 124 Auxiliary Packet Mode Configuration Register
(Block Base=0x0A00, Register Offset=0x08)
Field
Read /
Write
Bits
Length Reset
State
Description
HSTL_RX_TEST
R/W
0:0
1
0
Controls an internal test function in the HSTL receiver.
0: Normal operation
1: Reserved for internal IDT test
Table 125 Auxiliary HSTL Receiver Test Control Register
(Block Base=0x0A00, Register Offset=0x0E)
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